W42C32-05

更新时间： 2024-11-04 22:14:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器微控制器和处理器光电二极管
页数	文件大小	规格书
8页	134K
描述
Spread Spectrum Frequency Timing Generator

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中文翻译

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技术参数
数据手册

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W42C32-05 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.52
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP16,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	3.3/5 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	45 mA	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

W42C32-05 数据手册

W42C32-05

Spread Spectrum Frequency Timing Generator

Features

Key Specifications

• Maximized EMI suppression using Cypress’s Spread

Spectrum technology

• Generates a spread spectrum timing signal

• Reduces measured EMI by as much as 12 dB

• Integrated loop filter components

• Requires a single low-cost fundamental crystal (or

other frequency reference) for proper operation

• Special spread spectrum control functions

• Low-power CMOS design

Cycle-to-Cycle Jitter ....................................................250 ps

45/55 Duty Cycle.................................... approximately 1.4V

Selectable Frequency spread

2 ns rise/fall time 0.4V to 2.0V, 3.3V supply

2 ns rise/fall time 0.8V to 2.4V, 5.0V supply

Table 1. Frequency Spread Selection

W42C32-05

• Available in 16-pin SOIC package, (300 mil)

REFOUT

(MHz)

CLKOUT

(MHz)

VDD

(V)

FS2 FS1 FS0

Overview

22.1148

14.7456

44.2296 ±

2.5%

5.0

The W42C32 modulates the output of a single PLL in order to

‘spread’ the bandwidth of a synthesized clock and, more im-

portantly, decrease the peak amplitudes of its fundamental

harmonics. Since peak amplitudes are reduced, the radiated

electromagnetic emissions of the W42C32-05 are significantly

lower than the typical narrow band signal produced by oscilla-

tors and most frequency generators. Lowering a signal’s am-

plitude by increasing its bandwidth is a method of reducing

EMI called ‘spread spectrum frequency timing generation’.

This patented technique not only reduces the emissions of the

primary clock, but also impacts every signal synchronized to it.

44.2296

±1.5%

29.4912 ±

2.5%

18.432

14.318

18.432 ± 2.5%

66.66 – 2%

5.0

3.3

Reserved

14.318

100 – 2%

Reserved

Pin Configuration

SOIC

PD#

REFOUT

FS2

FS1

GND

SSON#

RESET

VDD

AGND

FS0

TEST

CLKOUT

AVDD

REFEN#

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

September 28, 1999, rev. **

12 3 4 5 6 7 8

中文翻译

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