Datasheet > 存储 > DRAM> W3H32M64E-400ESC

W3H32M64E-400ESC

更新时间： 2024-11-11 03:17:47

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
6页	231K
描述
32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package

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中文翻译

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数据手册

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W3H32M64E-400ESC 数据手册

W3H32M64E-XSBX

White Electronic Designs

ADVANCED*

32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package

FEATURES

ꢀ

Data rate = 667*, 533, 400

ꢀ

Write latency = Read latency - 1* tCK

ꢀ

Package:

Commercial, Industrial and Military Temperature

Ranges

• 208 Plastic Ball Grid Array (PBGA), 16 x 20mm

• 1.0mm pitch

ꢀ

Organized as 32M x 64, user conﬁgurable as 2 x

32M x 32

ꢀ

DDR2 Data Rate = 667*, 533, 400

Supply Voltage = 1.8V 0.1V

Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4-bit prefetch architecture

Weight: W3H32M64E-XSBX - 2.5 grams typical

BENEFITS

ꢀ

62% SPACE SAVINGS vs. FPBGA

Reduced part count

DLL for alignment of DQ and DQS transitions with

clock signal

42% I/O reduction vs FPBGA

Reduced trace lengths for lower parasitic

capacitance

ꢀ

Four internal banks for concurrent operation

(Per DDR2 SDRAM Die)

ꢀ

Suitable for hi-reliability applications

ꢀ

Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes

On Die Termination (ODT)

Upgradeable to 64M x 64 density (contact factory

for information)

* This product is under development, is not qualiﬁed or characterized and is subject

to change or cancellation without notice.

Adjustable data – output drive strength

Programmable CAS latency: 3, 4 or 5

Posted CAS additive latency: 0, 1, 2, 3 or 4

FIGURE 1 – DENSITY COMPARISONS

Actual Size

CSP Approach (mm)

W3H32M64E-XSBX

11.0

FBGA

19.0

Area

4 x 209mm²= 836mm²

4 x 90 balls = 360 balls

320mm²

62%

42%

I/O

208 Balls

Count

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

October 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6

中文翻译

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