Datasheet > W3EG6462S262D3F

W3EG6462S262D3F

更新时间： 2024-11-01 17:54:15

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
12页	195K
描述
DRAM,

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中文翻译

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数据手册

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W3EG6462S262D3F 数据手册

W3EG6462S-D3

White Electronic Designs

ADVANCED*

512MB – 2x32Mx64 DDR SDRAM UNBUFFERED

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG6462S is a 2x32Mx64 Double Data Rate

SDRAM memory module based on 256Mb DDR SDRAM

components. The module consists of sixteen 32Mx8 DDR

SDRAMs in 66 pin TSOP packages mounted on a 184 pin

FR4 substrate.

ꢀ

DDR200, DDR266, DDR333 and DDR400

• JEDEC design speciﬁed

ꢀ

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change or cancellation without notice.

Serial presence detect

Power supply:

• V_CC= V_CCQ= +2.5V 0.2V (100, 133 and 166

MHz)

• V_CC= V_CCQ= +2.6V 0.1V (200 MHz)

Standard 184 pin DIMM package

• PCB height: 30.48 (1.20") MAX

ꢀ

NOTE: Consult factory for availability of:

• Lead-free products

• Vendor source control option

• Industrial temperature option

OPERATING FREQUENCIES

DDR400 @CL=3 DDR333 @CL=2.5 DDR266 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2

Clock Speed

CL-t_RCD-t_RP

200MHz

3-3-3

166MHz

2.5-3-3

133MHz

2-3-3

133MHz

2-3-3

133MHz

2.5-3-3

100MHz

2-2-2

January 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...12

中文翻译

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