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W24L01S-70LL PDF预览

W24L01S-70LL

更新时间: 2024-09-25 22:06:15
品牌 Logo 应用领域
华邦 - WINBOND /
页数 文件大小 规格书
11页 184K
描述
128K X 8 CMOS STATIC RAM

W24L01S-70LL 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP32,.56针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32JESD-609代码:e3
长度:20.45 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:3/3.3 V
认证状态:Not Qualified座面最大高度:3 mm
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.04 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:11.3 mm
Base Number Matches:1

W24L01S-70LL 数据手册

 浏览型号W24L01S-70LL的Datasheet PDF文件第2页浏览型号W24L01S-70LL的Datasheet PDF文件第3页浏览型号W24L01S-70LL的Datasheet PDF文件第4页浏览型号W24L01S-70LL的Datasheet PDF文件第5页浏览型号W24L01S-70LL的Datasheet PDF文件第6页浏览型号W24L01S-70LL的Datasheet PDF文件第7页 
W24L01  
´ 8 CMOS STATIC RAM  
128K  
GENERAL DESCRIPTION  
The W24L01 is a normal-speed, very low-power CMOS static RAM organized as 131072 ´ 8 bits that  
operates on a wide voltage range from 2.7V to 3.6V power supply. The W24L01 family, W24L01-LE  
and W24L01-LI, can meet the requirement of various operating temperature. This device is  
manufactured using Winbond's high performance CMOS technology.  
FEATURES  
· Battery back-up operation capability  
· Data retention voltage: 1.5V (min.)  
· Packaged in 32-pin 450 mil SOP, standard type  
one TSOP (8 mm ´ 20 mm), small type one  
TSOP (8 mm ´ 13.4 mm) and 48-pin CSP  
· Low power consumption  
· Access time: 55 nS /70 nS  
· 2.7V to 3.6V supply voltage  
· Fully static operation  
· All inputs and outputs directly TTL compatible  
· Three-state outputs  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
CLK GEN.  
PRECHARGE CKT.  
V
NC  
A16  
A14  
1
2
3
4
5
6
7
8
9
10  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
DD  
A16  
A14  
A1  
CS2  
A12  
A7  
WE  
A1  
A
A12  
A4  
R
O
W
A6  
CORE CELL ARRAY  
1024 ROWS  
32-pin  
SOP  
A5  
A9  
A3  
A4  
A1  
D
E
C
O
D
E
R
A3  
OE  
128 X 8 COLUMNS  
A2  
A7  
A6  
A5  
A9  
A2  
A10  
CS  
A1  
11  
12  
13  
14  
I/O8  
I/O7  
I/O6  
A0  
I/O1  
I/O2  
I/O3  
Vss  
15  
16  
I/O5  
I/O4  
I/O1  
:
I/O8  
I/O CKT.  
COLUMN DECODER  
DATA  
CNTRL.  
1
2
3
4
5
6
7
A11  
A9  
A8  
32  
31  
30  
29  
28  
27  
26  
OE  
CLK  
A10  
GEN.  
CS1  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A13  
A15  
A8A1A0  
A13 A11A10  
WE  
WE  
CS2  
A15  
VDD  
NC  
A16  
A14  
A12  
A7  
CS1  
CS2  
32-pin  
TSOP  
8
9
10  
11  
12  
25  
24  
23  
OE  
V
SS  
I/O3  
I/O2  
I/O1  
A0  
A1  
A2  
A3  
22  
21  
20  
19  
18  
17  
PIN DESCRIPTION  
13  
14  
15  
16  
A6  
A5  
A4  
SYMBOL  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
A0 - A16  
I/O1 - I/O8  
48-pin CSP TOP VIEW  
Chip Select Input  
CS, CS2  
WE  
1
2
3
4
5
6
A
B
C
D
E
F
A0  
A1  
A2  
CS2  
A3  
A4  
A5  
A6  
A7  
A8  
Write Enable Input  
Output Enable Input  
I/O5  
I/O6  
I/O1  
I/O2  
WE  
NC  
V
V
V
SS  
CC  
OE  
VDD  
VSS  
NC  
V
CC  
SS  
I/O3  
NC  
I/O7  
I/O8  
A9  
NC  
Power Supply  
Ground  
No Connection  
G
H
A16 A15 I/O4  
A12 A13 A14  
OE  
CS1  
A11  
A10  
Publication Release Date: January 2, 2002  
Revision A6  
- 1 -  

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