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W24L04B-70LE PDF预览

W24L04B-70LE

更新时间: 2024-11-14 20:37:11
品牌 Logo 应用领域
华邦 - WINBOND 静态存储器内存集成电路
页数 文件大小 规格书
11页 153K
描述
Standard SRAM, 512KX8, 70ns, CMOS, CSP-36

W24L04B-70LE 技术参数

生命周期:Obsolete零件包装代码:CSP
包装说明:,针数:36
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.59
最长访问时间:70 ns内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-20 °C
组织:512KX8并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
技术:CMOS温度等级:OTHER
Base Number Matches:1

W24L04B-70LE 数据手册

 浏览型号W24L04B-70LE的Datasheet PDF文件第2页浏览型号W24L04B-70LE的Datasheet PDF文件第3页浏览型号W24L04B-70LE的Datasheet PDF文件第4页浏览型号W24L04B-70LE的Datasheet PDF文件第5页浏览型号W24L04B-70LE的Datasheet PDF文件第6页浏览型号W24L04B-70LE的Datasheet PDF文件第7页 
W24L04  
512K ´ 8 CMOS STATIC RAM  
GENERAL DESCRIPTION  
´
The W24L04 is a normal-speed, very low-power CMOS static RAM organized as 524288  
8 bits  
that operates on a wide voltage range from 2.7V to 3.3V power supply. The W24L04, W24L04-LE and  
W24L04-LI, can meet the requirement of various operating temperature. This device is manufactured  
using Winbond's high performance CMOS technology.  
FEATURES  
·
·
·
·
·
·
·
·
·
Low power consumption  
Access time: 70 nS  
2.7V to 3.3V supply voltage  
Fully static operation  
All inputs and outputs directly TTL compatible  
Three-state outputs  
Battery back-up operation capability  
Data retention voltage: 1.5V (min.)  
Packaged in 32-pin 450 mil SOP, standard  
´
type one TSOP (8 mm  
one TSOP (8 mm 13.4 mm) and 36 pin CSP  
BLOCK DIAGRAM  
PRECHARGE CKT.  
CLK GEN.  
32  
31  
30  
29  
28  
1
2
VDD  
A15  
A17  
A18  
A16  
A18  
A17  
3
4
A14  
A16  
WE  
A13  
A8  
A12  
A7  
R
5
6
O
A15  
A14  
CORE CELL ARRAY  
1024 ROWS  
W
27  
26  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
7
A9  
A11  
D
E
C
O
D
E
R
32-pin  
SOP  
25  
24  
23  
22  
512 X 8 COLUMNS  
A13  
A12  
8
9
OE  
10  
A10  
A10  
A8  
11  
12  
CS  
21  
20  
19  
18  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
I/O1  
I/O2  
I/O3  
13  
14  
A7  
15  
16  
I/O1  
:
I/O8  
I/O CKT.  
COLUMN DECODER  
DATA  
CNTRL.  
V
SS  
17  
CLK  
GEN.  
A9 A6 A5 A4 A3 A2 A1A0  
A11  
1
2
3
4
A11  
A9  
A8  
A13  
WE  
WE  
32  
OE  
A10  
31  
30  
29  
28  
27  
26  
CS  
CS  
OE  
I/O8  
I/O7  
I/O6  
5
6
A17  
A15  
VDD  
A18  
A16  
A14  
I/O5  
I/O4  
VSS  
I/O3  
I/O2  
I/O1  
A0  
A1  
7
8
25  
24  
23  
22  
21  
20  
19  
18  
32-pin  
TSOP  
9
10  
11  
12  
PIN DESCRIPTION  
A12  
A7  
A6  
A5  
A4  
13  
14  
15  
16  
SYMBOL  
DESCRIPTION  
Address Inputs  
A2  
A3  
17  
-
A0 A18  
Data Inputs/Outputs  
Chip Select Input  
-
I/O1 I/O8  
36-pin CSP TOP VIEW  
CS  
WE  
OE  
1
2
3
4
5
6
Write Enable Input  
Output Enable Input  
Power Supply  
Ground  
NC  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A8  
A
I/O5  
I/O6  
VSS  
VCC  
I/O1  
I/O2  
VCC  
VSS  
I/O3  
I/O4  
A7  
WE  
NC  
B
C
D
E
DD  
V
A17  
A16  
A12  
A18  
I/O7  
F
G
H
A15  
A13  
OE  
A10  
CS  
A11  
I/O8  
A9  
SS  
V
A14  
NC  
No Connection  
Publication Release Date: January 2000  
Revision A2  
- 1 -  

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