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W183GT PDF预览

W183GT

更新时间: 2024-11-09 19:50:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 124K
描述
Clock Generator, 75MHz, CMOS, PDSO14, 0.150 INCH, PLASTIC, SOIC-14

W183GT 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
其他特性:CAN ALSO OPERATE AT 5V SUPPLYJESD-30 代码:R-PDSO-G14
长度:8.65 mm端子数量:14
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:75 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE主时钟/晶体标称频率:75 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

W183GT 数据手册

 浏览型号W183GT的Datasheet PDF文件第2页浏览型号W183GT的Datasheet PDF文件第3页浏览型号W183GT的Datasheet PDF文件第4页浏览型号W183GT的Datasheet PDF文件第5页浏览型号W183GT的Datasheet PDF文件第6页浏览型号W183GT的Datasheet PDF文件第7页 
W183  
Full Feature Peak Reducing EMI Solution  
Features  
Table 1. Modulation Width Selection  
Cypress PREMIS™ family offering  
• Generates an EMI optimized clocking signal at the out-  
put  
• Selectable output frequency range  
• Single 1.25%, 3.75% down or center spread output  
• Integrated loop filter components  
• Operates with a 3.3 or 5V supply  
• Low power CMOS design  
W183  
W183-5  
Output  
SS%  
Output  
0
F
in Fout Fin  
Fin + 0.625% Fin≥  
0.625%  
1.25%  
1
F
in Fout Fin  
Fin + 1.875% Fin≥  
1.875%  
3.75%  
Table 2. Frequency Range Selection  
• Available in 14-pin SOIC (Small Outline Integrated  
Circuit)  
FS2  
0
FS1  
0
Frequency Range  
Key Specifications  
28 MHz FIN 38 MHz  
38 MHz FIN 48 MHz  
46 MHz FIN 60 MHz  
58 MHz FIN 75 MHz  
0
1
Supply Voltages:...........................................VDD = 3.3V±5%  
or VDD = 5V±10%  
1
0
Frequency Range: ............................ 28 MHz Fin 75 MHz  
Crystal Reference Range:................. 28 MHz Fin 40 MHz  
Cycle to Cycle Jitter: ....................................... 300 ps (max.)  
Selectable Spread Percentage:....................1.25% or 3.75%  
Output Duty Cycle: ............................... 40/60% (worst case)  
Output Rise and Fall Time: .................................. 5 ns (max.)  
1
1
Simplified Block Diagram  
Pin Configuration  
3.3V or 5.0V  
SOIC  
FS2  
CLKIN or X1  
NC or X2  
GND  
REFOUT  
OE#  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
X1  
SSON#  
Reset  
VDD  
XTAL  
Input  
X2  
Spread Spectrum  
Output  
(EMI suppressed)  
W183  
GND  
40 MHz  
Max  
VDD  
SS%  
FS1  
8
CLKOUT  
3.3V or 5.0V  
Oscillator or  
Reference Input  
Spread Spectrum  
W183  
Output  
(EMI suppressed)  
PREMIS is a trademark of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07158 Rev. **  
Revised September 25, 2001  

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