Datasheet > W162-19G

W162-19G

更新时间： 2024-11-20 23:41:23

品牌	Logo	应用领域
其他 - ETC		时钟驱动器输出元件
页数	文件大小	规格书
7页	134K
描述
NINE DISTRIBUTED-OUTPUT CLOCK DRIVER\|CMOS\|SOP\|16PIN\|PLASTIC

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W162-19G 数据手册

W162

Spread Aware™, Zero Delay Buffer

Features

Table 1. Input Logic

• Spread Aware™—designed to work with SSFTG

reference signals

SEL1 SEL0

QA0:3

QB0:3

PLL

QFB

Three-

State

Three-

State

Shutdown Active

• Two banks of four outputs, plus the fed back output

• Outputs may be three-stated

• Available in 16-pin SOIC or SSOP package

• Extra strength output drive available (-19 version)

• Internal feedback

Active

Three-

State

Active,

Utilized

Active

Shutdown, Active

Bypassed

Key Specifications

Active

Active,

Utilized

Active

Operating Voltage: ............................................... 3.3V±10%

Operating Range: ................................15 < f_OUT< 133 MHz

Cycle-to-Cycle Jitter: .................................................. 250 ps

Output to Output Skew: ............................................. 150 ps

Propagation Delay: ..................................................... 150 ps

Block Diagram

Pin Configuration

QFB

REF

QA0

QA1

VDD

GND

QB0

QB1

SEL1

QFB

QA3

QA2

VDD

GND

QB3

QB2

SEL0

REF

PLL

MUX

QA0

QA1

QA2

SEL0

SEL1

QA3

QB0

QB1

QB2

QB3

Spread Aware is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07150 Rev. **

Revised November 14, 2001

12 3 4 5 6 7

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