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W167BH

更新时间: 2024-11-25 19:32:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 178K
描述
Processor Specific Clock Generator, 160MHz, CMOS, PDSO48, 0.300 INCH, MO-118AA, SSOP-48

W167BH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, MO-118AA, SSOP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.83其他特性:ALSO REQUIRES 3.3V SUPPLY
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:160 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大压摆率:160 mA
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W167BH 数据手册

 浏览型号W167BH的Datasheet PDF文件第2页浏览型号W167BH的Datasheet PDF文件第3页浏览型号W167BH的Datasheet PDF文件第4页浏览型号W167BH的Datasheet PDF文件第5页浏览型号W167BH的Datasheet PDF文件第6页浏览型号W167BH的Datasheet PDF文件第7页 
PRELIMINARY  
W167B  
133-MHz Spread Spectrum FTG for Pentium® II Platforms  
Duty Cycle: ................................................................ 45/55%  
Features  
Spread Spectrum Modulation:................................... ±0.25%  
• Maximized EMI Suppression using Cypress’s Spread  
Spectrum technology  
• Three copies of CPU outputs selectable frequency  
• Three copies of 3V66 selectable frequency output at  
3.3V  
CPU to 3V66 Output Offset:............. 0.0–1.5 ns (CPU leads)  
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)  
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)  
Table 1. Pin Selectable Frequency  
• Ten copies of PCI clocks (selectable frequency), 3.3V  
SEL133/  
CPU 3V66 PCI IOAPIC  
• One double strength 14.318-MHz reference output at  
3.3V  
100# SEL2 SEL1 SEL0 MHz MHz MHz MHz  
• One copy of 48-MHz USB clock  
• One copy of selectable 24-/48-MHz for SIO  
• One copy of CPU-divide-by-2 output as reference input  
to Direct Rambus™ Clock Generator (Cypress W134)  
• Three copies of IOAPIC  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.3 66.7 33.3 16.7  
138 69 34.5 17.3  
143 71.5 35.8 17.9  
148  
150  
74  
37  
18.5  
75 37.5 18.8  
152.5 76.3 38.1 19.1  
155 77.5 38.8 19.4  
• Available in 48-pin SSOP (300 mils)  
Key Specifications  
160  
80  
40  
20  
100.2 66.8 33.4 16.7  
Supply Voltages: ...................................... V  
V
= 2.5V±5%  
= 3.3V±5%  
DDQ2  
DDQ3  
105  
114  
120  
70  
76  
80  
35  
38  
40  
17.5  
19  
20  
CPU, CPUdiv2 Output Jitter:....................................... 250 ps  
CPU, CPUdiv2 Output Skew:...................................... 175 ps  
IOAPIC, 3V66 Output Skew:....................................... 250 ps  
PCI0:8 Pin to Pin Skew:.............................................. 500 ps  
66.8 66.8 33.4 16.7  
124 82.7 41.3 20.7  
128.5 64.3 32.1 16.1  
133.9 67 33.5 16.7  
Pin Configuration[1]  
Block Diagram  
VDDQ3  
X1  
X2  
XTAL  
OSC  
REF2X  
IOAPIC2  
REF2X  
VDDQ3  
X1  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
2
VDDQ2  
IOAPIC0  
IOAPIC1  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDDQ2  
X2  
GND  
SEL2*/PCI0  
SEL1*/PCI1  
VDDQ3  
PCI2  
GND  
CPU_[0:2]  
3
VDDQ2  
CPUdiv2  
GND  
VDDQ2  
CPU2  
GND  
VDDQ2  
CPU1  
CPU0  
SDATA  
VDDQ3  
GND  
÷2  
CPUdiv2  
VDDQ3  
SEL133/100#  
PCI3  
PCI4  
PCI5  
GND  
PCI6  
PCI7  
VDDQ3  
PCI8  
PCI9  
PLL 1  
3V66_[0:2]  
÷2/÷1.5  
3
PCI0/SEL2*  
PCI1/SEL1*  
PWRDN#*  
SCLK  
VDDQ3  
GND  
÷2  
PCI_[2:9]  
PWRDWN#  
3V66_0  
3V66_1  
3V66_2  
VDDQ3  
SIO/24_48#MHz  
48MHz/SEL0*  
GND  
*
8
3
Power  
Down  
Logic  
VDDQ2  
SEL133/100#  
÷2  
IOAPIC[0:2]  
Note:  
QVD#DQ3  
1. Internal 250-kpull-up resistors present on inputs marked with *.  
Design should not rely solely on internal pull-up resistor to set I/O  
pins HIGH.  
PLL2  
48MHz/SEL0*  
÷2  
SIO/24_48#MHz  
SDATA  
SCLK  
Serial  
Logic  
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 2, 1999  

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