W149HT

更新时间： 2024-02-15 11:22:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	159K
描述
Processor Specific Clock Generator, 124MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48

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W149HT 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.49
其他特性：	ALSO REQUIRES AT 2.5V SUPPLY	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	15.875 mm
湿度敏感等级：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	124 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	220
主时钟/晶体标称频率：	14.318 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

W149HT 数据手册

W149

Upon W149 power-up, the first 2 ms of operation is used for

input logic selection. During this period, the four I/O pins (7,

25, 26, 46) are three-stated, allowing the output strapping re-

sistor on the l/O pins to pull each pin and its associated capac-

itive clock load to either a logic HIGH or LOW state. At the end

of the 2-ms period, the established logic “0” or “1” condition of

the l/O pin is latched. Next the output buffer is enabled, con-

verting the l/O pins into operating clock outputs. The 2-ms tim-

Overview

The W149 was developed as a single chip device to meet the

clocking needs of the Intel 440BX AGPset. In addition to the

typical outputs provided by standard 100-MHz 440BX AGPset

FTGs, the W149 adds a thirteen output buffer, supporting

SDRAM DIMM modules in conjunction with the chipset.

Cypress proprietary spread spectrum frequency synthesis

technique is a feature of the CPU and PCI outputs. This feature

reduces the peak EMI measurements of not only the output

signals and their harmonics, but also of any other clock signals

that are properly synchronized to them.

er starts when V

reaches 2.0V. The input bits can only be

reset by turning V off and then back on again.

It should be noted that the strapping resistors have no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of clock output is <40Ω (nominal), which is minimally af-

Functional Description

fected by the 10-kΩ strap to ground or V . As with the series

termination resistor, the output strapping resistor should be

placed as close to the l/O pin as possible in order to keep the

interconnecting trace short. The trace from the resistor to

I/O Pin Operation

Pins 7, 25, 26, 46 are dual-purpose l/O pins. Upon power-up

these pins act as logic inputs, allowing the determination of

assigned device functions. A short time after power-up, the

logic state of each pin is latched and the pins become clock

outputs. This feature reduces device pin count by combining

clock outputs with input select pins.

ground or V should be kept less than two inches in length to

prevent system noise coupling during input logic sampling.

When the clock outputs are enabled following the 2-ms input

period, the specified output frequency is delivered on the pin,

assuming that V has stabilized. If V has not yet reached

full value, output frequency initially may be below target but will

increase to target once V voltage has stabilized. In either

case, a short output clock cycle may be produced from the

CPU clock outputs when the outputs are enabled.

An external 10-kΩ “strapping” resistor is connected between

the l/O pin and ground or V . Connection to ground sets a

latch to “0”, connection to V sets a latch to “1”. Figure 1 and

Figure 2 show two suggested methods for strapping resistor

connections.

V_DD

10 kΩ

Clock Load

W149

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 kΩ

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

Output Strapping Resistor

Series Termination Resistor

10 kΩ

Clock Load

W149

Output

Buffer

Power-on

Reset

Timer

Resistor Value R

Hold

Output

Low

Output Three-state

Data

Latch

Figure 2. Input Logic Selection Through Jumper Option

1 234 5 6 7...14

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