W149HT

更新时间： 2024-01-16 14:02:26

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	159K
描述
Processor Specific Clock Generator, 124MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48

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W149HT 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.49
其他特性：	ALSO REQUIRES AT 2.5V SUPPLY	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	15.875 mm
湿度敏感等级：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	124 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	220
主时钟/晶体标称频率：	14.318 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

W149HT 数据手册

W149

Pin Definitions

Pin Name

Pin No.

Pin Type

Pin Description

CPU0:1

44, 43

CPU Clock Outputs: See Tables 2 and 6 for detailed frequency information. Output

voltage swing is controlled by voltage applied to VDDQ2.

PCI1:5

8, 10, 11, 12,

PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by

the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied

to VDDQ3.

PCI_F/MODE

I/O

Fixed PCI Clock Output: Frequency is set by the FS0:1 inputs or through serial

input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP#

input. Upon power-up the mode input will be latched, which will determine the func-

tion of pin 2, REF0/(PCI_STOP#). See Table 1.

Output Enable Input: When brought LOW, all outputs are placed in a high-imped-

ance state. When brought HIGH, all clock outputs activate.

IOAPIC

48MHz/FS0

IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage

swing is controlled by VDDQ2.

I/O

48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this

output can be used as the reference for the Universal Serial Bus. Upon power-up,

FS0 input will be latched, which will set clock frequencies as described in Table 2.

This output does not have the Spread Spectrum feature.

24MHz/FS1

REF1/FS2

I/O

24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this

output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input

will be latched, which will set clock frequencies as described in Table 2. This output

does not have the Spread Spectrum feature.

I/O Dual-Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched

which will set clock frequencies as described in Table 2. When an output, this pin

provides a fixed clock signal equal in frequency to the reference signal provided at

the X1/X2 pins.

REF0/

(PCI_STOP#)

Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function is determined by the

MODE input. When set as an input, the PCI_STOP# input enables the PCI 1:5

outputs when HIGH and causes them to remain at logic 0 when LOW. The

PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on

the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal

equal in frequency to the reference signal provided at the X1/X2 pins.

SDRAMIN

Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs

(SDRAM0:12).

SDRAM0:12

38, 37, 35,

34, 32, 31,

29, 28, 21,

20, 18, 17, 40

Buffered Outputs: These thirteen dedicated outputs provide copies of the signal

provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deacti-

vated when CLK_STOP# input is set LOW.

SCLK

SDATA

I/O

Clock pin for I C circuitry.

Data pin for I C circuitry.

Crystal Connection or External Reference Frequency Input: This pin has dual

functions. It can be used as an external 14.318-MHz crystal connection or as an

external reference frequency input.

Crystal Connection: An input connection for an external 14.318-MHz crystal. If

using an external reference, this pin must be left unconnected.

VDDQ3

1, 6, 14, 19,

27, 30, 36

Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,

PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to

3.3V supply.

VDDQ2

GND

42, 48

Power Connection: Power supply for IOAPIC and CPU0:1 output buffers. Connect

to 2.5V, or 3.3V.

3, 9, 16, 22,

33, 39, 45

Ground Connections: Connect all ground pins to the common system ground

plane.

123 4 5 6 7...14

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