W149HT

更新时间： 2024-02-16 21:56:30

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	159K
描述
Processor Specific Clock Generator, 124MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48

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W149HT 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.49
其他特性：	ALSO REQUIRES AT 2.5V SUPPLY	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	15.875 mm
湿度敏感等级：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	124 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	220
主时钟/晶体标称频率：	14.318 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

W149HT 数据手册

W149

chipset. Clock device register changes are normally made

upon system initialization, if any are required. The interface

can also be used during system operation for power manage-

ment functions. Table 3 summarizes the control functions of

the serial data interface.

Serial Data Interface

The W149 features a two-pin, serial data interface that can be

used to configure internal register settings that control partic-

ular device functions. Upon power-up, the W149 initializes with

default register settings, therefore the use of this serial data

interface is optional. The serial interface is write-only (to the

clock chip) and is the dedicated function of device pins SDATA

and SCLOCK. In motherboard applications, SDATA and

SCLOCK are typically driven by two logic outputs of the

Operation

Data is written to the W149 in eleven bytes of eight bits each.

Bytes are written in the order shown in Table 4.

Table 3. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled.

Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI

and system power. Examples are clock

outputs to unused PCI slots.

CPU Clock Frequency

Selection

Provides CPU/PCI frequency selections through

software. Frequency is changed in a smooth and

controlled fashion.

For alternate microprocessors and power

management options. Smooth frequency

transition allows CPU frequency change

under normal system operation.

Output Three-state

(Reserved)

Puts clock output into a high-impedance state.

Production PCB testing.

Reserved function for future device revision or

production device testing.

No user application. Register bit must be

written as 0.

Table 4. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

Slave Address

11010010

Commands the W149 to accept the bits in Data Bytes 0–6 for internal

mon serial data bus, it is necessary to have a specific slave address for

each potential receiver. The slave receiver address for the W149 is

11010010. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver).

Command Code

Byte Count

Don’t Care

Unused by the W149, therefore bit values are ignored (“Don’t Care”).

This byte must be included in the data write sequence to maintain prop-

er byte allocation. The Command Code Byte is part of the standard

serial communication protocol and may be used when writing to anoth-

er addressed slave receiver on the serial data bus.

Don’t Care

Unused by the W149, therefore bit values are ignored (“Don’t Care”).

This byte must be included in the data write sequence to maintain prop-

er byte allocation. The Byte Count Byte is part of the standard serial

communication protocol and may be used when writing to another ad-

dressed slave receiver on the serial data bus.

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Refer to Table 5

The data bits in Data Bytes 0–7 set internal W149 registers that control

device operation. The data bits are only accepted when the Address

Byte bit sequence is 11010010, as noted above. For description of bit

control functions, refer to Table 5, Data Byte Serial Configuration Map.

1 2 3 456 7 8...14

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