Datasheet > W134M_05

W134M_05

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
12页	208K
描述
Direct Rambus⑩ Clock Generator

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数据手册

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W134M_05 数据手册

W134M/W134S

Device Characteristics

Parameter

t_CYCLE

Description

Min.

2.5

–

Max.

3.75

100

160

–

Unit

Clock Cycle Time

t_J

Cycle-to-Cycle Jitter at Clk/ClkB^[9]

Total Jitter over 2, 3, or 4 Clock Cycles^[9]

266-MHz Cycle-to-Cycle Jitter^[10]

266-MHz Total Jitter over 2, 3, or 4 Clock Cycles^[10]

Phase Aligner Phase Step Size (at Clk/ClkB)

–

t_STEP

t_ERR,PD

Phase Detector Phase Error for Distributed Loop Measured at

–100

100

PclkM-SynclkN (rising edges) (does not include clock jitter)

t_ERR,SSC

V_X,STOP

V_X

V_COS

V_OH

V_OL

r_OUT

I_OZ

I_OZ,STOP

PLL Output Phase Error when Tracking SSC

Output Voltage during Clk Stop (StopB=0)

Differential Output Crossing-Point Voltage

Output Voltage Swing (p-p single-ended)^[11]

Output High Voltage

–100

1.1

1.3

0.4

–

1.0

–

250

–

100

2.0

1.8

0.6

2.0

–

500

Output Low voltage

Output Dynamic Resistance (at pins)^[12]

Output Current during Hi-Z (S0 = 0, S1 = 1)

Output Current during Clk Stop (StopB = 0)

Output Duty Cycle over 10,000 Cycles

Output Cycle-to-Cycle Duty Cycle Error

Output Rise and Fall Times (measured at 20%–80% of output voltage)

Ω

µA

%t_CYCLE

t_DC,ERR

t_R,t_F

t_CR,CF

500

100

Difference between Output Rise and Fall Times on the Same Pin of a

Single Device (20%–80%)

Notes:

9. Output Jitter spec measured at t

10. Output Jitter Spec measured at t

= 2.5 ns.

CYCLE

= 3.75 ns.

11. V

= V –V

OH OL.

COS

12. r

= DV / D I . This is defined at the output pins.

O O

OUT

Document #: 38-07426 Rev. *C

Page 9 of 12

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