Datasheet > W134M_05

W134M_05

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
12页	208K
描述
Direct Rambus⑩ Clock Generator

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数据手册

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W134M_05 数据手册

W134M/W134S

Timing Diagrams

Power-down Exit and Entry

PwrDnB

Clk/ClkB

POWERDN

POWERUP

Output Enable Control

STOP

StopB

CLKON

CLKOFF

CLKSETL

Clk/ClkB

Output clock

not specified

glitches may

occur

Clock output settled within

50 ps of the phase before

disabled

Clock enabled

and glitch-free

Figure 5. State Transition Timing Diagrams

Mult0 and/or Mult1

Clk/ClkB

t_MULT

Figure 6. Multiply Transition Timing

Table 8. State Transition Latency Specifications

Transition Latency

Transition

From

Parameter

Max.

Description

Power-down

Normal

t_POWERUP

3 ms

Time from PwrDnB to Clk/ClkB output settled

(excluding t_DISTLOCK).

Power-down

Clk Stop

Test

t_POWERUP

t_MULT

3 ms

1 ms

Time from PwrDnB until the internal PLL and clock has

turned ON and settled.

Time from PwrDnB to Clk/ClkB output settled

(excluding t_DISTLOCK).

V_DDON

Normal

Clk Stop

Test

Time from V_DDis applied and settled until Clk/ClkB

output settled (excluding t_DISTLOCK).

Time from V_DDis applied and settled until internal PLL

and clock has turned ON and settled.

Time from V_DDis applied and settled until internal PLL

and clock has turned ON and settled.

Normal

Time from when Mult0 or Mult1 changed until Clk/ClkB

output resettled (excluding t_DISTLOCK).

Document #: 38-07426 Rev. *C

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