Datasheet > W134M_05

W134M_05

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
12页	208K
描述
Direct Rambus⑩ Clock Generator

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W134M_05 数据手册

W134M/W134S

Table 8. State Transition Latency Specifications (continued)

Transition Latency

Transition

From

Parameter

Max.

Description

Clk Stop

Normal

t_CLKON

10 ns Time from StopB until Clk/ClkB provides glitch-free

clock edges.

Clk Stop

Normal

t_CLKSETL20 cycles Time from StopB to Clk/ClkB output settled to within 50

ps of the phase before CLK/CLKB was disabled.

Normal

Test

Clk Stop

Normal

t_CLKOFF

t_CTL

5 ns

3 ms

Time from StopB to Clk/ClkB output disabled.

Time from when S0 or S1 is changed until CLK/CLKB

output has resettled (excluding t_DISTLOCK).

Normal

Test

t_CTL

3 ms

1 ms

Time from when S0 or S1 is changed until CLK/CLKB

output has resettled (excluding t_DISTLOCK).

Time from PwrDnB to the device in Power-down.

B,D

Normal or Clk Stop Power-down t_POWERDN

Figure 5 shows that the Clk Stop to Normal transition goes

through three phases. During t_CLKON, the clock output is not

specified and can have glitches. For t_CLKON< t < t_CLKSETL, the

clock output is enabled and must be glitch-free. For

t > t_CLKSETL, the clock output phase must be settled to within

50 ps of the phase before the clock output was disabled. At

this time, the clock output must also meet the voltage and

timing specifications of the Device Characteristics table. The

outputs are in a high-impedance state during the Clk Stop

mode.

Table 9. Distributed Loop Lock Time Specification

Parameter

Description

Min.

Max.

Unit

t_DISTLOCKTime from when Clk/ClkB output is settled to when the phase error between SynclkN and

PclkM falls within the t_ERR,PDspec in Table .

Table 10.Supply and Reference Current Specification

Parameter

I_POWERDOWN

I_CLKSTOP

I_NORMAL

I_REF,PWDN

I_REF,NORM

Description

Min.

Max.

250

100

Unit

µA

“Supply” current in Power-down state (PwrDnB 1 = 0)

“Supply” current in Clk Stop state (StopB = 0)

“Supply” current in Normal state (StopB = 1, PwrDnB = 1)

Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)

Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)

–

Document #: 38-07426 Rev. *C

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