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VSC8101JA PDF预览

VSC8101JA

更新时间: 2024-11-11 20:57:59
品牌 Logo 应用领域
VITESSE ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
14页 171K
描述
Telecom Circuit, 1-Func, GAAS, PQCC28, 0.454 X 0.454 INCH, PLASTIC, LCC-28

VSC8101JA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.22JESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.5316 mm
功能数量:1端子数量:28
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2 V认证状态:Not Qualified
座面最大高度:3.91 mm子类别:ATM/SONET/SDH ICs
最大压摆率:0.19 mA标称供电电压:2 V
表面贴装:YES技术:GAAS
电信集成电路类型:TELECOM CIRCUIT温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.5316 mm
Base Number Matches:1

VSC8101JA 数据手册

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VSC8101/8102  
VITESSE  
155.52 Mb/s Clock and  
Data Recovery Units  
Preliminary Data Sheet  
Features  
• Recovers Clock and Data at STS-3 (155.52 Mb/s)  
Data Rate.  
• ECL or Psuedo ECL (PECL) Differential Inputs  
and Outputs.  
• No External Components Required.  
• Maximum Power Dissipation:  
VSC8101: 400mW,  
VSC8102: 3W.  
• Available in One-channel (VSC8101) or  
Eight-channel (VSC8102) Versions.  
• Single 2V Power Supply  
• Recovers Data from NRZ or NRZI Data Streams.  
• Available in 28PLCC (VSC8101)  
and 100PQFP (VSC8102)  
• No Output Clock Drift in Absence of Data  
Transitions Once Lock is Acquired.  
Functional Description  
The VSC8101 and VSC8102 are clock and data recovery units for STS-3 (155.52 Mb/s) applications. They  
implement the complete clock and data recovery functions and require no external components. The one-chan-  
nel device, VSC8101, accepts serial data in NRZ or NRZI format and re-times the data using a sampling clock  
extracted from the input data stream. The recovered clock (RCLK+/-) and re-timed data (RDAT+/-) are pre-  
sented at the serial output ports, aligned such that the falling edge of the recovered clock (RCLK+) coincides  
with the center of the data eye (see figure 4). The VSC8102 is an octal version of the VSC8101. A single refer-  
ence clock input (REFCK+/-) at the STS-3 data rate (155.52MHz) is required for either device. The data and  
reference clock inputs, and the recovered data and clock outputs are differential ECL levels referenced to the  
VCC supply. Only one supply, +2V or -2V, is required for operation.  
Both the VSC8101 and VSC8102 employ a digital clock extraction technique, and do not contain a conven-  
tional PLL. As a result, the spectrum of the jitter in the recovered clock and data is non-Gaussian. Peak-to-peak  
jitter of RCLK+/- is ± 400 ps or less. The data input rate to the devices is required to be within ± 30 ppm from  
the reference clock frequency. The devices have data input jitter accommodation up to 3.2ns, half the data  
period. The VSC8101and VSC8102 also provide an input which control the loop bandwidth of the clock extrac-  
tion function.  
Tracking Frequency Bandwidth Control  
The tracking of the recovered clock and data to the frequency variation of the input data stream can be  
adjusted in the VSC8101 and VSC8102. In particular, the FILTER0 input controls the degree to which the inter-  
nal clock can track the input data frequency. The effect is equivalent to controlling the loop bandwidth of a con-  
ventional PLL-based clock recovery system. Equivalent bandwidths of 150 KHz and 10 KHz can be selected.  
The FILTER0 input truth data is shown in the AC Characteristic Table.  
Jitter Tolerance  
The VSC8101 and VSC8102 are designed to meet the BellcoreGR-253-CORE, section 5.6.2.2.2 Jitter Tol-  
erance specification.  
Figure 1: Jitter Tolerance Mask for STS-3  
Jitter Amplitude  
(UI p-p)  
15  
1.5  
0.15  
10 30  
300  
6.5K  
65K  
Frequency (Hz)  
G52087-0 Rev. 1.3  
® VITESSE Semiconductor Corporation  
Page 1  

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