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VSC8114 PDF预览

VSC8114

更新时间: 2024-02-14 22:09:23
品牌 Logo 应用领域
VITESSE 时钟发生器异步传输模式ATM
页数 文件大小 规格书
24页 437K
描述
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

VSC8114 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:HQFP, QFP100,.7X.9针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
应用程序:ATM;SDH;SONETJESD-30 代码:R-PQFP-G100
长度:20 mm功能数量:1
端子数量:100最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HQFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK, HEAT SINK/SLUG
电源:3.3,3.3/5 V认证状态:Not Qualified
座面最大高度:3.4 mm子类别:ATM/SONET/SDH ICs
标称供电电压:3.3 V表面贴装:YES
技术:GAAS电信集成电路类型:ATM/SONET/SDH MUX/DEMUX
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

VSC8114 数据手册

 浏览型号VSC8114的Datasheet PDF文件第2页浏览型号VSC8114的Datasheet PDF文件第3页浏览型号VSC8114的Datasheet PDF文件第4页浏览型号VSC8114的Datasheet PDF文件第5页浏览型号VSC8114的Datasheet PDF文件第6页浏览型号VSC8114的Datasheet PDF文件第7页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Data Sheet  
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux  
with Integrated Clock Generation and Clock Recovery  
VSC8114  
Features  
Operates at STS-12/STM-4 (622.08Mb/s)  
Data Rate  
• Loss of Signal (LOS) Input & LOS Detection  
• +3.3V/5V Programmable PECL Serial Interface  
• Compatible with Industry ATM UNI Devices  
• Provides Equipment, Facilities and Split Loop-  
back Modes as well as Loop Timing Mode  
• On Chip Clock Generation of the 622.08MHz  
High Speed Clock (Mux)  
• Provide PECL Reference Clock Inputs  
• On Chip Clock Recovery of the 622.08MHz  
High Speed Clock (Demux)  
• Meets Bellcore, ITU and ANSI Specifications  
for Jitter Performance  
• 8-Bit Parallel TTL Interface with Parity Error  
Detection and Generation  
• Low Power - 0.9Watts Typical  
• 100 PQFP Package  
• SONET/SDH Frame Recovery  
General Description  
The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication  
Unit (PLL) for high speed clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serial-  
to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direc-  
tion (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer  
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-  
ment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat  
spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for  
ATM physical layers and SONET/SDH systems applications.  
Functional Description  
The VSC8114 is designed to provide a SONET/SDH compliant interface between the high speed optical  
networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8114  
converts 8 bit parallel data at 77.76Mb/s to a serial bit stream at 622.08Mb/s. The device also provides a Facility  
Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly  
to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to gen-  
erate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76  
MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing  
the entire part to a single clock. The block diagram on page 2 shows the major functional blocks associated with  
the VSC8114.  
The receive section provides the serial-to-parallel conversion, converting 622Mb/s bit stream to an 8 bit par-  
allel output at 77.76MHz. A Clock Recovery Unit (CRU) is integrated into the receive circuit to recover the high  
speed clock from the received serial data stream. The receive section provides an Equipment Loopback function  
which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel out-  
puts. The VSC8114 also provides the option of selecting between either its internal CRU’s clock and data sig-  
nals, or optics containing a CRU clock and data signals. The receive section also contains a SONET/SDH frame  
G52185-0, Rev 4.0  
11/1/99  
VITESSE SEMICONDUCTOR CORPORATION  
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896  
Page 1  

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