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VSC7216UC-01

更新时间： 2024-01-24 13:39:47

品牌	Logo	应用领域
VITESSE		电信集成电路电信电路
页数	文件大小	规格书
38页	548K
描述
Multi-Gigabit Interconnect Chip

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中文翻译

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技术参数
数据手册

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VSC7216UC-01 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 1.27 MM PITCH, BGA-256	针数：	256
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	功能数量：	1
端子数量：	256	最高工作温度：	95 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA256,20X20,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	0.925 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	OTHER	端子面层：	TIN LEAD SILVER
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	27 mm	Base Number Matches：	1

VSC7216UC-01 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

Multi-Gigabit Interconnect Chip

VSCV7S2C1672-0116

corresponds to a valid Fibre Channel data stream. The PSDETn and RSDETn output timing is identical to the

low-speed receiver outputs, as selected by RMODE(1:0). See Table 6.

Receiver Equalization

Incoming data on the PRX/RRX inputs typically contains a substantial amount of Inter Symbol Interference

(ISI) or deterministic jitter which reduces the ability of the receiver to recover data without errors. An equalizer

has been added to each of the receiver’s input buffers in order to compensate for this deterministic jitter. This

circuit has been designed to effectively reduce the ISI commonly found in copper cables or backplane traces due

to low frequencies traveling faster than high frequencies as a result of the skin effect. The equalizer boosts high

frequency edge response in order to reduce the adverse effects of ISI.

Clock and Data Recovery

At the receiver, each channel contains an independent Clock Recovery Unit (CRU) which accepts the

selected serial input source, extracts the high-speed clock and retimes the data. Each CRU automatically locks

on data and if the data is not present, will automatically lock to the REFCLK. This maintains a very well-

behaved recovered clock, RCLKn/RCLKNn which does not contain any slivers and will operate at a frequency

of the REFCLK reference ±200 ppm. The use of an external Lock-to-Reference pin is not needed.

The Clock Recovery Unit must perform bit synchronization which occurs when the CRU locks onto and

properly samples the incoming serial data as described in the previous paragraph. When the CRU is not locked

onto the serial data, the 10-bit data out of the decoder is invalid which results in numerous 8B/10B decoding

errors or disparity errors. When the link is disturbed (e.g., the cable is disconnected or the serial data source is

switched), the CRU will require a certain amount of time to lock onto data which is specified in the AC Timing

Characteristics for “Data Acquisition Lock Time.”

Deserializer and Character Alignment

The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit

“Comma” pattern (‘0011111xxx’ or ‘1100000xxx’) is recognized by the receiver and allows it to identify the

10-bit character boundary. Note that this pattern is found in three special characters, K28.1, K28.5 and K28.7,

however, K28.5 is chosen as the unique IDLE character. Only K28.1 and K28.5 should be used in normal

operation. The K28.7 character should be reserved for test and characterization use.

Character alignment occurs when the deserializer synchronizes the 10-bit character framing boundary to a

“Comma” pattern in the incoming serial data stream. If the receiver identifies a “Comma” pattern in the

incoming data stream which is misaligned to the current framing boundary the receiver will re-synchronize the

recovered data in order to align the data to the new “Comma” pattern. Re-synchronization ensures that the

“Comma” character is output on the internal 10-bit bus so that bits 0 through 9 equal ‘0011111xxx’ or

‘1100000xxx’. If the “Comma” pattern is aligned with the current framing boundary, re-synchronization will

not change the current alignment. Re-synchronization is always enabled and cannot be turned off when ENDEC

is HIGH. After character re-synchronization the VSC7216-01 ensures that within a link, the 8-bit data sent to

the transmitting VSC7216-01 will be recovered by the receiving VSC7216-01 in the same bit locations as the

transmitter (i.e., Tn(7:0) = Rn(7:0)). When ENDEC is LOW, “Comma” detection and alignment are enabled

only if KCHAR is HIGH.

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 8

G52352-0, Rev 3.2

05/05/01

1...5 6 789 10 11...38

中文翻译

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与VSC7216UC-01相关器件

型号	品牌	获取价格	描述	数据表
VSC7216UC-02	VITESSE	获取价格	Telecom Circuit, 1-Func, PBGA256, 27 X 27 MM, 1.27 MM PITCH, BGA-256
VSC7216UI-06	VITESSE	获取价格	Telecom IC, PBGA256,
VSC7216XUC-02	VITESSE	获取价格	Telecom IC, PBGA256
VSC7216XUC-06	VITESSE	获取价格	Telecom IC, PBGA256,
VSC7216XUI-06	VITESSE	获取价格	Telecom IC, PBGA256
VSC7217	VITESSE	获取价格	Multi-Gigabit Interconnect Chip
VSC7217UC	VITESSE	获取价格	Multi-Gigabit Interconnect Chip
VSC7226	VITESSE	获取价格	Quad 3.125Gb/s Backplane Transceiver
VSC7226-01	MICROSEMI	获取价格	Ethernet Transceiver, PBGA256, 21 MM, BGA-256
VSC7226-02	MICROSEMI	获取价格	Ethernet Transceiver, PBGA256, 21 MM, BGA-256

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