VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datas heet
Multi-Gigabit Interconnect Chip
VSC7217
Features
• Compatible with VSC7211/7212/7214
• 4 ANSI X3T11 Fibre Channel and IEEE
802.3z Gigabit Ethernet Compliant Trans-
ceivers
• Fast-Locking CRU: 100-Bit Clock Periods
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• Over 8 Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• PECL Rx Signal Detect and Cable Equalization
• 8B/10B Encoder/Decoder per Channel,
Optional Encoder/Decoder Bypass Operation
• Per-Channel Serial Tx-to-Rx and Parallel Rx-to-
Tx Internal Loopback Modes
• “ASIC-FriendlyTM” Timing Options for
Transmitter Parallel Input Data
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• Elastic Buffers for Intra/Inter-Chip Cable
Deskewing and Channel-to-Channel Align-
ment
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 3.0W Typ, 3.5W Max.
• 256-pin, 27mm BGA Package
• Tx/Rx Rate Matching via IDLE Insertion/
Deletion
VSC7217 Block Diagram
TRANSMITTER
RECEIVER
LBEND(1:0)
8
RD(7:0)
PTXEND
8
RXP/RD
LBTXD
8B/10B
Decode
Elastic
Buffer
10
10
10
10
IDLED
KCHD
ERRD
8
8
8
8
8
8
8
8
3
TD(7:0)
C/DD
WSEND
Clk/Data
Recovery
PTXD+ PRXD+
PTXD- PRXD-
RTXD+ RRXD+
RTXD- RRXD-
8B/10B
Encode
D Q
D Q
D Q
D Q
10
10
10
10
RCLKD
RCLKDN
PSDETD
RSDETD
RTXEND
PTXENC
LBENC(1:0)
RXP/RC
8
8
8
RC7:0)
8
3
LBTXC
8B/10B
Decode
Elastic
Buffer
IDLEC
KCHC
ERRC
TC(7:0)
C/DC
WSENC
Clk/Data
Recovery
PTXC+ PRXC+
PTXC- PRXC-
RTXC+ RRXC+
RTXC- RRXC-
8B/10B
Encode
RCLKC
RCLKCN
PSDETC
RSDETC
RTXENC
PTXENB
LBENB(1:0)
RXP/RB
RB(7:0)
8
3
LBTXB
8B/10B
Decode
Elastic
Buffer
IDLEB
KCHB
ERRB
TB(7:0)
C/DB
WSENB
Clk/Data
Recovery
PTXB+ PRXB+
8B/10B
Encode
PTXB- PRXB-
RTXB+ RRXB+
RCLKB
RCLKBN
RTXB- RRXB-
PSDETB
RSDETB
RTXENB
PTXENA
LBENA(1:0)
RXP/RA
RA(7:0)
8
3
LBTXA
8B/10B
Decode
Elastic
Buffer
IDLEA
KCHA
ERRD
TA(7:0)
C/DA
WSENA
Clk/Data
Recovery
PTXA+ PRXA+
PTXA- PRXA-
RTXA+ RRXA+
RTXA- RRXA-
8B/10B
Encode
RCLKA
RCLKAN
PSDETA
RSDETA
KCHAR
RTXENA
WSI
WSO
Channel
Align
4
FLOCK
TBCA
TBCB
TBCC
TBCD
Tx Clock
REFCLK
x20/x10
DUAL
Clock Gen
TBERRA
TRSTN
TMS
JTAG
RESETN
ENDEC
BIST
TBERRB
TBERRC
TBERRD
TMODE(2:0)
RMODE(1:0)
REFCLKP
REFCLKN
Boundary
TDO
TDI
CAP0 CAP1
Scan
TCK
G52325-0, Rev. 3.0
6/14/00
Ó VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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