Datasheet > VSC7321VH

VSC7321VH

更新时间： 2024-11-11 20:10:35

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
2页	450K
描述
Micro Peripheral IC,

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技术参数
数据手册

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VSC7321VH 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.65
Base Number Matches：	1

VSC7321VH 数据手册

PHYSICAL LAYER PRODUCT

ETHERNET PRODUCT

VSC7321

™

VSC7321 Meigs-II - 10 x 1G and 10G Ethernet MAC Chip

S P E C I F I C A T I O N S :

ꢀImplemented in low Power 0.18 micron CMOS Technology, 2.5V/3.3V IO

ꢀIndustrial Temperature Range (-40ºC to +85ºC)

ꢀStandard 5-Pin P1149.1 JTAG Test Port

ꢀPackaged in a 728 pin TBGA

A P P L I C A T I O N S :

ꢀEnterprise and Metro Ethernet Switches

ꢀMulti-Service Provisioning Platforms

ꢀMetro SONET/SDH Transport (ADMs)

ꢀEdge and Core Aggregation Routers

ꢀDWDM Transport Terminals (Wavelength Routers)

F E A T U R E S :

ꢀTen Triple-Speed Ethernet MACs w/Support for RGMII/GMII/MII

ꢀIntegrated GbE SERDES for Direct Connection to Optical Modules

ꢀIntelligent VLAN and MPLS Identification

A P P L I C A T I O N D I A G R A M S :

ꢀLoss less flow Control in Metro Applications up to 10km

10 x GbE MAC interfacing to NPU or ASIC

10 x GbE MAC w/

RGMII/GMII

ꢀ10GbE MAC w/Integrated XAUI SERDES Interface Compliant

to IEEE 802.3ae

PHY

Switch or

Transceiver

NPU or

VSC7321

ASIC

ꢀLow Pin Count, low Power OIF SPI-4.2 System Interface

ꢀExtensive Loopback Capabilities for Both Line and System Side

ꢀConfigurable Parallel or Serial CPU Interface

ꢀDual MIIM Interface for Managing PHY Devices

ꢀIndependent Egress and Ingress Shaping/Policing

ꢀRate Limiting in 1 Mb/s Increments

PHY

SPI-4.2

Backplane or

Switch Interface

RGMII/GMII

10 x GbE over SONET/SDH using the VSC9118

10 x GbE MAC w/

Integrated Serdes

Packet Mapper

with VC and GFP

STS-1

Grooming TSI

O/E

VSC9118

VSC9185

VSC7321

O/E

ꢀ802.3ad Compliant Link Aggregation and Trunking

Serial

SPI-4.2

Backplane

Interface

ꢀStatistical Support for RMON 1 (RFC2819), IEEE 802.3 Annex

30A, and SNMP (RFC 1213, 1573, and 1643)

10 GbE MAC interfacing to NPU or ASIC

10 GbE MAC w/

Integrated XAUI

ꢀSupports Both Minimum Size 64B Frames as well as 9600B

Jumbo Frames

Switch or

Transceiver

NPU or

O/E

VSC7321

ASIC

ꢀAutomatic Generation of PAUSE Frames Based on Programmable

Per Port FIFO Watermarks

XAUI

SPI-4.2

Backplane or

Switch Interface

PB-VSC7321-002

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