VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datas heet
Mutli-Gigabit Interconnect Chip
VSC7217
four transmit channel inputs for serialization will be transferred on the receive channel parallel outputs. The
Word Sync Sequence provides a unique synchronization point in the serial data stream that is used to align the
receive channels. This sequence consists of 16 consecutive K28.5 IDLE characters with disparity reversals on
the second and fourth characters. The Word Sync Sequence is sent either as “I+ I+ I- I- I+ I- I+ I- I+ I- I+ I- I+
I- I+ I-” or as “I- I- I+ I+ I- I+ I- I+ I- I+ I- I+ I- I+ I- I+”, depending on the transmitter’s running disparity at the
time the first IDLE character is serialized.
Transmission of the Word Sync Sequence is initiated independently in each channel when the WSENn
input is asserted HIGH for one character time (see Figure 5). When WSENn is HIGH, the C/Dn and Tn(7:0)
inputs are ignored. The WSENn, C/Dn and Tn(7:0) inputs are also ignored for the subsequent 15 character
times. In Figure 5 below, the Word Sync Sequence is initiated in cycle W1 and transmitted through cycle W16.
Normal data transmission (or the transmission of another Word Sync Sequence) resumes in cycle D3. Figure 5
is drawn assuming that input timing is referenced to REFCLK (e.g., TMODE(2:0)=000) with the DUAL input
LOW. As long as WSENn remains asserted, another Word Sync Sequence will be generated.
Figure 5: Word Sync Sequence Generation
D1
D2
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 D3
D4
REFCLK
WSENn
C/Dn
Tn(7:0) 0x01 0x02 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX 0x03 0x04
TXn+/-
D1.0+ D2.0+ K28.5+ K28.5+ K28.5- K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- D3.0+ D4.0-
Serializer
The 10-bit output from the encoder (or from the encoder input register if ENDEC is LOW) is fed into a
multiplexer which serializes the parallel data using the synthesized transmit clock. The least significant bit of
the 10B data is transmitted first. Each channel has both primary and redundant serial output ports, PTXn and
RTXn, respectively, which consists of differential PECL output buffers operating at either 10 or 20 times the
REFCLK rate. The primary and redundant transmitter outputs are controllable separately on each channel. The
primary PECL outputs (PTXn) are enabled when the PTXENn input is HIGH, and the redundant PECL outputs
(RTXn) are enabled when the RTXENn input is HIGH. When a PECL output is disabled, the associated output
buffers do not consume power and the attached pins are undriven.
Receiver Functional Des cription
Serial Data Source
Each receive channel has both primary (PTXn) and redundant (RRXn) serial input ports, which consists of
differential PECL input buffers. Each channel also has a control input, RXP/Rn, used to select either the pri-
Page 6
Ó VITESSE SEMICONDUCTOR CORPORATION
G52325-0, Rev. 3.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
6/14/00
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