Datasheet > VSC7217

VSC7217

更新时间： 2022-09-12 00:09:29

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VITESSE		/
页数	文件大小	规格书
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Multi-Gigabit Interconnect Chip

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VSC7217 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datas heet

Multi-Gigabit Interconnect Chip

VSC7217

Trans mitter Functional Des cription

Transmitter Data Bus

Each VSC7217 transmit channel has an 8-bit input transmit data character, Tn(7:0), and two control inputs,

C/Dn and WSENn. The C/Dn input determines whether a normal data character or a special “K-character” is

transmitted, and the WSENn input initiates transmission of a 16-character “Word Sync Sequence” used to align

the receive channels. These data and control inputs are clocked either on the rising edge of REFCLK, on the

rising edge of TBCn, or within the data eye formed by TBCn. When not using REFCLK, each channel uses

either its own TBCn input, or the TBCA input. The transmit interface mode is controlled by TMODE(2:0), as

shown in Table 1.

When used, the TBCn inputs must be frequency locked to REFCLK. No phase relationship is assumed. A

small skew buffer is provided to tolerate phase drift between TBCn and REFCLK. This buffer is recentered by

the RESETN input, and the total phase drift after recentering must be limited to ±180° (where 360° is one char-

acter time). Each channel has an error output, TBERRn, that is asserted HIGH to indicate that the phase drift

between TBCn and REFCLK has accumulated to the point that the elastic limit of the skew buffer has been

exceeded and a transmit data character has been either dropped or duplicated. This error can not occur when

input timing is referenced to REFCLK. The TBERRn output timing is identical to the low-speed receiver out-

puts, as selected by RMODE(1:0) in Table 5.

Table 1: Transmit Interface Input Timing Mode

TMODE(2:0)

0 0 0

Input Timing Reference

REFCLK Rising Edge

0 0 1

0 1 0

0 1 1

Reserved

1 0 0

1 0 1

1 1 0

1 1 1

TBCA Rising Edge

TBCn Rising Edge

TBCA Data Eye

TBCn Data Eye

The following figures show the possible relationships between data and control inputs and the selected

input timing source. Figure 2 shows how REFCLK is used as an input timing reference. This mode of opera-

tion is used in the VSC7211 and VSC7214. Figure 3 and Figure 4 show how TBCn is used as an input timing

reference. When TBCn is used to define a data eye (see Figure 4), it functions as an additional data input that

simply toggles every cycle.

Note that the REFCLK and TBCn inputs are not used directly to clock the input data. Instead, an internal

PLL generates edges aligned with the appropriate clock. The arrows on the rising edges of these signals define

the reference edge for the internal phase detection logic. An internal clock is generated at 1/10 the serial trans-

G52325-0, Rev. 3.0

6/14/00

Ó VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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