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VSC7216UC-01

更新时间： 2024-01-26 11:25:29

品牌	Logo	应用领域
VITESSE		电信集成电路电信电路
页数	文件大小	规格书
38页	548K
描述
Multi-Gigabit Interconnect Chip

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数据手册

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VSC7216UC-01 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 1.27 MM PITCH, BGA-256	针数：	256
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	功能数量：	1
端子数量：	256	最高工作温度：	95 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA256,20X20,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	0.925 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	OTHER	端子面层：	TIN LEAD SILVER
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	27 mm	Base Number Matches：	1

VSC7216UC-01 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

Multi-Gigabit Interconnect Chip

VSC7216-01

Serializer

The 10-bit output from the encoder (or from the encoder input register if ENDEC is LOW) is fed into a

multiplexer which serializes the parallel data using the synthesized transmit clock. The least significant bit of

the 10B data is transmitted first. Each channel has both primary and redundant serial output ports, PTXn and

RTXn respectively, which consist of differential PECL output buffers operating at either 10 or 20 times the

REFCLK rate. The primary and redundant transmitter outputs are separately controllable on each channel. The

primary PECL outputs PTXn are enabled when the PTXENn input is HIGH, and the redundant PECL outputs

RTXn are enabled when the RTXENn input is HIGH. When a PECL output is disabled, the associated output

buffers do not consume power and the attached pins are un-driven. The PECL outputs do not require external

resistors.

Receiver Functional Description

Serial Data Source

Each receive channel has both primary and redundant serial input ports, PRXn and RRXn, respectively,

which consist of differential PECL input buffers. Each channel also has a control input, RXP/Rn, used to select

either the primary or redundant serial input as the data source for that channel. When RXP/RC is HIGH, the C

channel serial data source is PRXC. When LBENn(1:0)=10, the channel’s transmitter is looped back and

becomes the serial data source regardless of the state of RXP/Rn (see Table 5).

Table 5: Serial Data Source Selection

LBENn(1:0)

RXP/Rn

Serial Data Source

≠ 1 0

RRXn

PRXn

LBTXn

Loopback fromTransmitters

= 1 0

Signal Detection

Each channel’s primary and redundant PECL input buffers have an associated signal detect output,

PSDETn and RSDETn. All eight outputs are available for continuous monitoring of both the selected and non-

selected input. Each signal detect output is asserted HIGH when transitions are detected on the associated PECL

input and the signal amplitude exceeds 200mV under nominal operating conditions. A LOW indicates that

either no transitions are detected or the signal amplitude is below 100mV under nominal operating conditions.

The signal detect outputs are considered undefined when the signal amplitude is in the 100mV to 200mV range.

The signal detect circuitry behaves like a re-triggerable one-shot that is triggered by signal transitions, and

whose time-out interval ranges from 40 to 80 bit times. The transition density is not checked to make sure that it

G52352-0, Rev 3.2

05/05/01

Page 7

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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与VSC7216UC-01相关器件

型号	品牌	描述	获取价格	数据表
VSC7216UC-02	VITESSE	Telecom Circuit, 1-Func, PBGA256, 27 X 27 MM, 1.27 MM PITCH, BGA-256	获取价格
VSC7216UI-06	VITESSE	Telecom IC, PBGA256,	获取价格
VSC7216XUC-02	VITESSE	Telecom IC, PBGA256	获取价格
VSC7216XUC-06	VITESSE	Telecom IC, PBGA256,	获取价格
VSC7216XUI-06	VITESSE	Telecom IC, PBGA256	获取价格
VSC7217	VITESSE	Multi-Gigabit Interconnect Chip	获取价格

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