Datasheet > 电信电路 > 其他电信集成电路> VSC7216UC-01

VSC7216UC-01

更新时间： 2024-01-22 21:17:16

品牌	Logo	应用领域
VITESSE		电信集成电路电信电路
页数	文件大小	规格书
38页	548K
描述
Multi-Gigabit Interconnect Chip

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技术参数
数据手册

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VSC7216UC-01 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 1.27 MM PITCH, BGA-256	针数：	256
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	功能数量：	1
端子数量：	256	最高工作温度：	95 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA256,20X20,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	0.925 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	OTHER	端子面层：	TIN LEAD SILVER
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	27 mm	Base Number Matches：	1

VSC7216UC-01 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

Multi-Gigabit Interconnect Chip

VSCV7S2C1672-0116

When used, the TBCn inputs must be frequency-locked to REFCLK. No phase relationship is assumed. A

small skew buffer is provided to tolerate phase drift between TBCn and REFCLK. This buffer is recentered by

the RESETN input, and the total phase drift after recentering must be limited to ±180° (where 360° is one

character time). Each channel has an error output, TBERRn, that is asserted HIGH to indicate that the phase

drift between TBCn and REFCLK has accumulated to the point that the elastic limit of the skew buffer has been

exceeded and a transmit data character has been either dropped or duplicated. This error can not occur when

input timing is referenced to REFCLK. The TBERRn output timing is identical to the low-speed receiver

outputs, as selected by RMODE(1:0) in Table 6.

Figures 2 through 4 show the possible relationships between data and control inputs and the selected input

timing source. Figure 2 shows how REFCLK is used as an input timing reference. This mode of operation is

used in the VSC7211 and VSC7214. Figure 3 and Figure 4 show how TBCn is used as an input timing

reference. When TBCn is used to define a data eye as shown in Figure 4, it functions as an additional data input

that simply toggles every cycle.

Note that the REFCLK and TBCn inputs are not used directly to clock the input data. Instead, an internal

Phase-Lock Loop (PLL) generates edges aligned with the appropriate clock. The arrows on the rising edges of

these signals define the reference edge for the internal phase detection logic. An internal clock is generated at

one-tenth the serial transmit data rate that is locked to the selected input timing source. This is an especially

important issue when DUAL is HIGH and input timing is referenced to REFCLK, since the falling edge is NOT

used. The internal clock active edges are placed coincident with the REFCLK rising edges and halfway between

the REFCLK rising edges in this mode.

A similar situation exists when TBCn is used to define a data eye, only the rising edges of TBCn are used to

define the external data timing. The internal clock active edges are placed at 90° and 270° points between

consecutive TBCn rising edges (which are assumed to be 360° apart).

Figure 2: Transmit Timing, TMODE(2:0) = 000

REFCLK

(DUAL = 0)

REFCLK

(DUAL = 1

)

Tn(7:0)

C/Dn

Valid

WSENn

Figure 3: Transmit Timing, TMODE(2:0) = 10X

TBCA

TBCn

Tn(7:0)

C/Dn

Valid

WSENn

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 4

G52352-0, Rev 3.2

05/05/01

1 2 345 6 7...38

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与VSC7216UC-01相关器件

型号	品牌	描述	获取价格	数据表
VSC7216UC-02	VITESSE	Telecom Circuit, 1-Func, PBGA256, 27 X 27 MM, 1.27 MM PITCH, BGA-256	获取价格
VSC7216UI-06	VITESSE	Telecom IC, PBGA256,	获取价格
VSC7216XUC-02	VITESSE	Telecom IC, PBGA256	获取价格
VSC7216XUC-06	VITESSE	Telecom IC, PBGA256,	获取价格
VSC7216XUI-06	VITESSE	Telecom IC, PBGA256	获取价格
VSC7217	VITESSE	Multi-Gigabit Interconnect Chip	获取价格

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