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VSC6282 PDF预览

VSC6282

更新时间: 2024-11-09 20:55:23
品牌 Logo 应用领域
VITESSE 逻辑集成电路延迟线
页数 文件大小 规格书
16页 124K
描述
Logic Circuit, GAAS, PQFP128, PLASTIC, QFP-128

VSC6282 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:QFP
包装说明:FQFP, QFP128,.67X.93,20针数:128
Reach Compliance Code:compliant风险等级:5.3
系列:VSC6JESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
逻辑集成电路类型:LOGIC CIRCUIT功能数量:1
端子数量:128最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP128,.67X.93,20封装形状:RECTANGULAR
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:-2,3.3 V最大电源电流(ICC):2560 mA
可编程延迟线:YESProp。Delay @ Nom-Sup:8 ns
认证状态:Not Qualified座面最大高度:3.4 mm
子类别:Delay Lines最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:GAAS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

VSC6282 数据手册

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VITESSE  
SEMICONDUCTOR CORPORATION  
Advance Product Information  
125MHz Octal Deskew  
VSC6280/81/82  
Features  
• Eight Adjustable Delay Lines in One Package  
• 750 ps Minimum Pulse Width  
• 125 MHz Bandwidth  
• Independent Delay Adjustments for Positive  
and Negative Going Transitions  
• Fully Digital. No Off-chip DACs Required  
• No Sensitive Analog Reference Voltages for  
Improved Crosstalk Performance.  
• Fanout Mode and Edge Mode Features  
Through Mask Programming  
• Dual Supply Operation -2, +3.3V  
• 128 PQFP Package  
• Up to 8ns of Delay with <10 psec  
LSB Resolution  
Functional Description  
The VSC6280, VSC6281, and VSC6282 are adjustable digital delay lines designed for high-precision delay  
adjustment of high frequency ECL signals. They are designed specifically for de-skewing multiple drive side  
channels on a shared resource ATE system. They integrate fully digital delay lines eliminating the requirement  
for off-chip components such as DAC’s, trim resistors and compensation capacitors. The three devices use a  
novel design to provide maximum timing stability and minimum part-to-part delay variation resulting in maxi-  
mum usable range in the de-skew of multiple timing paths.  
Two delay adjustments are available for each channel, Delay_R and Delay_F. These delay values indepen-  
dently adjust the rising-edge and falling edge of a pulse, respectively. Delay values are serially loaded into a  
Calibration Register via the Serial Data Input during system calibration. In addition there are 16 11-bit Data  
Latches for the 16 Delay Elements. ADR[3:0] determines which of the 16 Data latches is loaded from the Cali-  
bration Register. The Delay Registers hold an 11-bit word. This Delay value determines the TPDSPAN of the  
Variable Delay Element. The resolution of the Delay Element is 10ps.  
Configurational Description  
The VSC6280, VSC6281, and VSC6282 configurations are mask programmable as selected by the user, and  
described in the block diagrams, shown as Figure 1, 2, and 3. Table 1 below provides further specifications and  
operability for each part number.  
Table 1:VSC6280/81/82 Configurations  
Part No.  
Description  
Edge/Pulse Mode  
VSC6280  
VSC6281  
VSC6282  
Standard Configuration: 8 Input and 8 Output  
Edge Configuration: 16 Input and 16 Output  
Fanout Configuration: 1 Input and 8 Output  
Pulse  
Edge  
Pulse  
Note: Edge mode delays rising or falling edges. Pulse mode delays both rising and falling pulse edges independently.  
G52153-0, Rev. 2.2  
8/5/98  
VITESSE SEMICONDUCTOR CORPORATION  
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896  
Page 1  

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