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VSC6424 PDF预览

VSC6424

更新时间: 2024-11-18 21:53:31
品牌 Logo 应用领域
VITESSE 移位寄存器
页数 文件大小 规格书
18页 367K
描述
500 Mb/s Video Shift Register IC

VSC6424 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:HFQFP,针数:128
Reach Compliance Code:compliant风险等级:5.73
其他特性:ALSO REQUIRES 3.3V边界扫描:NO
外部数据总线宽度:10JESD-30 代码:R-PQFP-G128
长度:20 mm低功率模式:NO
端子数量:128最高工作温度:70 °C
最低工作温度:输出数据总线宽度:8
封装主体材料:PLASTIC/EPOXY封装代码:HFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, HEAT SINK/SLUG, FINE PITCH
认证状态:Not Qualified座面最大高度:3.4 mm
最大供电电压:-2.1 V最小供电电压:-1.9 V
标称供电电压:-2 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, VIDEO SHIFT REGISTERBase Number Matches:1

VSC6424 数据手册

 浏览型号VSC6424的Datasheet PDF文件第2页浏览型号VSC6424的Datasheet PDF文件第3页浏览型号VSC6424的Datasheet PDF文件第4页浏览型号VSC6424的Datasheet PDF文件第5页浏览型号VSC6424的Datasheet PDF文件第6页浏览型号VSC6424的Datasheet PDF文件第7页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Preliminary Datasheet  
500 Mb/s Video  
Shift Register IC  
VSC6424  
Features  
• Multiplex or Demultiplex Operation  
• ECL and TTL I/Os: ECL for high-speed interface,  
TTL for low-speed interface  
• Selectable Shift Register Length  
• Power Supplies: +3.3V and -2V @ 2.7 Watts (Max.)  
• 500Mb/s Operation using internal timing  
• 250Mb/s Operation using external timing  
• Functional Replacement for Bt424  
o
o
• Commercial (0 to +70 C) Temperature Range  
• Package: 14mm x 20mm 128 PQFP  
• External ECL Reference Voltage (-1.32 V)  
General Description  
The VSC6424 is a 500Mb/s video shift register IC that is based on a 40-bit user-configured shift register.  
The shift register may be used either as a multiplexer (parallel in, serial out) or as a demultiplexer (serial in, par-  
allel out). The VSC6424 can be configured into 8 5-bit, 8 4-bit, 5 8-bit, 4 10-bit, 2 16-bit, 2 20-bit, 1 32-bit, or 1  
40-bit shift register.  
VSC6424 Functional Block Diagram  
OEN  
HBLANK  
VBLANK  
5
A<0:4>  
AEN/RETIME  
SIN  
(ECL)  
40  
10  
8
DOUT<0:7>  
CLKOUT  
MUX  
40  
40  
Input  
Latch  
(TTL)  
SB<0:39>  
40-bit  
RSeghiisftter  
High  
Speed  
Interface  
(ECL)  
Low  
Speed  
Interface  
(TTL)  
3
S<0:2>  
MODE  
DE-  
MUX  
10  
DIN<0:9>  
INT/EXTN  
OPS  
LLDN  
SEN/DIVC  
SLDN/SYNC  
Clock  
Generator  
Phase  
Rotation  
CLKE(ECL)  
CLKT(TTL)  
CLK  
(ECL)  
3
SP<0:2>  
G52236-0, Rev 3.0  
7/13/99  
VITESSE SEMICONDUCTOR CORPORATION  
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896  
Page 1  

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