Datasheet > VS1003

VS1003

更新时间： 2024-11-20 21:55:47

品牌	Logo	应用领域
其他 - ETC		解码器编解码器
页数	文件大小	规格书
57页	454K
描述
MP3 / WMA AUDIO CODEC

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中文翻译

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数据手册

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VS1003 数据手册

VS1003

VS1003 PRELIMINARY

VS1003 - MP3/WMA AUDIO CODEC

Features

Description

• Decodes MPEG 1 & 2 audio layer III (CBR

VS1003 is a single-chip MP3/WMA/MIDI audio

decoder and ADPCM encoder. It contains a high-

performance, proprietary low-power DSP proces-

sor core VS DSP⁴, working data memory, 5 KiB

instruction RAM and 0.5 KiB data RAM for user

applications, serial control and input data inter-

faces, 4 general purpose I/O pins, an UART, as

well as a high-quality variable-sample-rate mono

ADC and stereo DAC, followed by an earphone

ampliﬁer and a ground buffer.

+VBR +ABR); WMA 4.0/4.1/7/8/9 all pro-

ﬁles (5-384kbps); WAV (PCM + IMA AD-

PCM);

General MIDI / SP-MIDI ﬁles

• Encodes IMA ADPCM from microphone

or line input

• Streaming support for MP3 and WAV

• Bass and treble controls

• Operates with a single clock 12..13 MHz.

• Internal PLL clock multiplier

• Low-power operation

VS1003 receives its input bitstream through a se-

rial input bus, which it listens to as a system slave.

The input stream is decoded and passed through a

digital volume control to an 18-bit oversampling,

multi-bit, sigma-delta DAC. The decoding is con-

trolled via a serial control bus. In addition to the

basic decoding, it is possible to add application

speciﬁc features, like DSP effects, to the user RAM

memory.

• High-quality on-chip stereo DAC with no

phase error between channels

• Stereo earphone driver capable of driving a

30 load

• Separate operating voltages for analog, dig-

ital and I/O

• 5.5 KiB On-chip RAM for user code / data

• Serial control and data interfaces

• Can be used as a slave co-processor

• SPI ﬂash boot for special applications

• UART for debugging purposes

• New functions may be added with software

and 4 GPIO pins

audio

mic

VS1003

audio

Mono

ADC

Stereo

DAC

Stereo Ear−

phone Driver

MIC AMP

MUX

line

audio

GPIO

output

GPIO

X ROM

X RAM

Y ROM

Y RAM

DREQ

Serial

Data/

SCLK

XCS

XDCS

Control

Interface

VSDSP

UART

Clock

multiplier

Instruction

RAM

Instruction

ROM

Version 0.92, 2005-06-07

12 3 4 5 6 7...57

中文翻译

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