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VPLD48J3E-100.00MHZ PDF预览

VPLD48J3E-100.00MHZ

更新时间: 2024-11-14 08:29:43
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CONNOR-WINFIELD /
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2页 188K
描述
LVPECL Output Clock Oscillator, 100MHz Nom

VPLD48J3E-100.00MHZ 数据手册

 浏览型号VPLD48J3E-100.00MHZ的Datasheet PDF文件第2页 
THE CONNOR-WINFIELD CORP.  
2111 COMPREHENSIVE DRIVE.  
AURORA, IL 60505.  
FAX (630) 851-5040.  
PHONE (630) 851-4722.  
HTTP://WWW.CONWIN.COM  
P R O D UC T D ATA S H E E T  
CRYSTAL CONTROLLED OSCILLATORS  
3.3V SURFACE MOUNT VCXO OSCILLATOR  
CW 0701  
VPLD48J3E  
100.00M  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
TABLE 1.0  
NOTE  
UNITS  
MINIMUM NOMINAL MAXIMUM  
UNITS  
°C  
Storage Temperature  
Supply Voltage  
-40  
-0.5  
-0.5  
-
-
-
85  
7.0  
7.0  
(Vcc)  
(Vc)  
Vdc  
Vdc  
Control Voltage  
VPLD48J3E  
OPERATING SPECIFICATIONS  
PARAMETER  
TABLE 2.0  
NOTE  
MINIMUM NOMINAL MAXIMUM  
UNITS  
DESCRIPTION  
100  
Center Frequency  
(Fo)  
-
360  
-
MHz  
ppm  
Total Frequency Tolerance  
Operating Temperature Range  
Supply Voltage  
-35  
-
35  
1
The Connor-Winfield  
-30  
-
70  
°C  
VPLD48J3E is a 3.3V Voltage  
Controlled Crystal Oscillator  
(VCXO) with LVPECL  
Differential outputs. The  
VPLD48J3E is designed for  
use with PLL systems  
requiring low jitter and tight  
stability.  
(Vcc)  
(Icc)  
3.135  
3.3  
-
3.465  
Vdc  
Supply Current  
-
-
-
-
-
-
-
-
-
100  
mA  
Jitter (BW=10Hz to 20MHz)  
Jitter (BW=12kHz to 80MHz)  
SSB Phase Noise at 10Hz offset  
SSB Phase Noise at 100Hz offset  
SSB Phase Noise at 1KHz offset  
SSB Phase Noise at 10KHz offset  
SSB Phase Noise at 100KHz offset  
SSB Phase Noise at 1 MHz offset  
-
5
1
-
ps rms  
ps rms  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
-
-50  
-80  
-110  
-135  
-140  
-145  
-
-
-
-
-
INPUT CHARACTERISTICS  
PARAMETER  
TABLE 3.0  
NOTE  
MINIMUM NOMINAL MAXIMUM  
UNITS  
Vdc  
ppm  
%
Control Voltage Range  
Absolute Pull Range (APR)  
Monotonic Linearity  
(Vc)  
0.3  
+/-50  
-10  
-
1.65  
3.0  
-
-
2
FEATURES  
-
10  
Input Impedance  
50K  
-
Ohm  
KHz  
Vdc  
Vdc  
3.3V OPERATION  
-
-
-
Modulation Bandwidth (3dB)  
Enable Input Voltage (Low)  
Disable Input Voltage (High)  
10  
-
1.68  
-
(Vil)  
-
3
3
LVPECL DIFFERENTIALOUTPUTS  
ENABLE / DISABLE FUNCTION  
LOW JITTER <1pS RMS  
(Vih)  
2.275  
LOW VOLTAGE PECL OUTPUT CHARACTERISTICS  
TABLE 4.0  
NOTE  
4
PARAMETER  
MINIMUM NOMINAL MAXIMUM  
UNITS  
Ohms  
Vdc  
LOAD  
-
2.275  
-
-
-
50  
-
TOTALFREQUENCY TOLERANCE:  
±35ppm  
Voltage  
(High)  
(Low)  
(Voh)  
(Vol)  
-
1.68  
55  
Vdc  
Duty Cycle at 50% Level  
45  
50  
%
TEMPERATURE RANGE: -30 to 70°C  
SURFACE MOUNT PACKAGE  
TAPEAND REEL PACKAGING  
PACKAGE CHARACTERISTICS  
TABLE 5.0  
Package  
Non-hermetic package consisting of an FR4 substrate with grounded metal  
cover.  
PROCESS RECOMMENDATIONS  
Solder Reflow  
TABLE 6.0  
The component solder used internal to this device has a m elting point of  
221°C. The peak temperature inside the device should be less than or  
equal to 220°C for a maximum of 10 seconds  
ORDERING INFORMATION  
Wash  
Notes  
Ultrasonic cleaning is not recommended.  
VPLD48J3E - 100.00MHz  
1.0  
Inclusive of calibration @ 25°C, frequency stability vs. temperature, s upply and load variations, shock, vibration and aging  
for ten years. Control voltage (Vc) = 1.65 Vdc.  
2.0  
3.0  
4.0  
Control voltage for (Fo) = 1.65 Vdc Typical. Positive Transfer Func tion.  
When oscillator is disabled the true output is in a low state (Vol) and the complementary output is in the high stat e (VoH)  
50 ohm termination into Vcc-2V or Thevein equivalent.  
VCXO  
SERIES  
CENTER  
FREQUENCY  
Specifications subject to change without notice.  
12/18/03  
Vx499  
1
2
01  
REV:  
Copyright 2001 Connor-Winfield all rights reserved.  
DATASHEET #:  
PAGE  
OF  
DATE:  
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