Datasheet > V62C1801024LL

V62C1801024LL

更新时间： 2024-10-13 22:41:31

品牌	Logo	应用领域
MOSEL		静态存储器
页数	文件大小	规格书
10页	94K
描述
Ultra Low Power 128K x 8 CMOS SRAM

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数据手册

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V62C1801024LL 数据手册

V62C1801024L(L)

Ultra Low Power

128K x 8 CMOS SRAM

Functional Description

Features

The V62C1801024L is a low power CMOS Static RAM or-

ganized as 131,072 words by 8 bits. Easy memory expansion

• Ultra Low-power consumption

- Active: 20mA at 70ns

- Stand-by: 5 mA (CMOS input/output)

1 mA CMOS input/output, L version

is provided by an active LOW CE1

, an active HIGH CE2, an

, and Tri-state I/O’s. This device has an a-

active LOW OE

utomatic power-down mode feature when deselected.

• Single +1.8V to 2.2V Power Supply

• Equal access and cycle time

Writing to the device is accomplished by taking Chip E-

) LOW, and Chip Ena-

nable 1 (CE1 ) with Write Enable (WE

ble 2 (CE2) HIGH. Reading from the device is performed by

) with Output Enable (OE)

taking Chip Enable 1 (CE1

• 70/85/100/150 ns access time

LOW while Write Enable (WE ) and Chip Enable 2 (CE2)

is HIGH. The I/O pins are placed in a high-impedance st-

ate when the device is deselected: the outputs are disabled

during a write cycle.

• Easy memory expansion with CE1, CE2

inputs

and OE

• 1.0V data retention mode

The V62C1801024LL comes with a 1V data retention feature

and Lower Standby Power. The V62C1801024L is available in

a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.

• TTL compatible, Tri-state input/output

• Automatic power-down when deselected

32-Pin TSOP1 / STSOP (See next page)

Logic Block Diagram

CE1

I/O

GND

I/O

INPUT BUFFER

A13

A¹

I/O8

I/O

A₃

A²

Vcc

1024

A₄

A⁵

A₅

A⁶

1024

A₆

A⁷

1024

I/O1

I/O

A₉

COLUMN DECODER

CONTROL

CE1

CIRCUIT

CONTROL

CE2

A11

A12

A13

A14

CE1

CE2

CIRCUIT

A11

A12

REV. 1.1 April 2001 V62C1801024L(L)

12 3 4 5 6 7...10

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