Datasheet > V62C1162048L(L)-70B

V62C1162048L(L)-70B

更新时间： 2024-10-13 22:34:03

品牌	Logo	应用领域
MOSEL		静态存储器
页数	文件大小	规格书
11页	110K
描述
Ultra Low Power 128K x 16 CMOS SRAM

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V62C1162048L(L)

Ultra Low Power

128K x 16 CMOS SRAM

Features

• Low-power consumption

- Active: 35mA I_CCat 70ns

Functional Description

The V62C1162048L is a Low Power CMOS Static

RAM organized as 131,072 words by 16 bits. Easy

Memory expansion is provided by an active LOW (CE)

and (OE) pin.

- Stand-by: 10 mA (CMOS input/output)

2 mA (CMOS input/output, L version)

• 70/85/100/120 ns access time

• Equal access and cycle time

• Single +1.8V to2.2V Power Supply

• Tri-state output

This device has an automatic power-down mode feature

when deselected. Separate Byte Enable controls (BLE

and BHE) allow individual bytes to be accessed. BLE

controls the lower bits I/O1 - I/O8. BHE controls the

upper bits I/O9 - I/O16.

Writing to these devices is performed by taking Chip

Enable (CE) with Write Enable (WE) and Byte Enable

(BLE/BHE) LOW.

• Automatic power-down when deselected

• Multiple center power and ground pins for

improved noise immunity

Reading from the device is performed by taking Chip

Enable (CE) with Output Enable (OE) and Byte Enable

• Individual byte controls for both Read and

Write cycles

(BLE/BHE) LOW while Write Enable (WE

) is held

• Available in 44 pin TSOPII / 48-fpBGA / 48-mBGA

HIGH.

Logic Block Diagram

TSOPII / 48-fpBGA / 48-mBGA (See nest page)

Pre-Charge Circuit

Vcc

Vss

Memory Array

1024 X 2048

BHE

BLE

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A16

A15

A14

A13

A12

Data

Cont

I/O1 - I/O8

I/O Circuit

Data

Cont

I/O9 - I/O16

Column Select

A10 A11 A12 A13 A14 A15 A16

A10

A11

BHE

BLE

REV. 1.2 May 2001 V62C1162048L(L)

12 3 4 5 6 7...11

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