Datasheet > V58C265164S

V58C265164S

更新时间： 2022-11-27 16:17:42

品牌	Logo	应用领域
MOSEL		动态存储器双倍数据速率
页数	文件大小	规格书
44页	451K
描述
64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

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V58C265164S 数据手册

MOSEL VITELIC

V58C265164S

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs

CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to

make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not

defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.

The mode register is written by asserting low on CS, RAS, CAS, WE and BA (The DDR SDRAM should be

in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins

A ~ A in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock

cycles are required to meet t

spec. The mode register contents can be changed using the same com-

MRD

mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-

ister is divided into various fields depending on functionality. The burst length uses A ~ A , addressing mode

uses A , CAS latency (read latency from column address) uses A ~ A . A is a Mosel Vitelic specific test

mode during production test. A is used for DLL reset. A must be set to low for normal MRS operation. Refer

to the table for specific codes for various burst length, addressing modes and CAS latencies.

1. MRS can be issued only at all banks precharge state.

2. Minimum tRP is required to issue MRS command.

Address Bus

BA1

BA 0

A11

A10

I/O DLL

Extended Mode Register

Mode Register

MRS

RFU : Must be set "0"

DLL TM CAS Latency

RFU

Burst Length

I/O Strength

Full

DLL Enable

Enable

DLL Reset

Burst Type

Sequential

mode

Normal

Test

Half

Disable

Yes

Interleave

Burst Length

CAS Latency

Latency

BA0

An ~ A0

A6 A5

Latency

Reserve

Sequential

Reserve

Interleave

Reserve

(Existing)MRS Cycle

Extended Funtions(EMRS)

Reserve

2.5

Reserve

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

Reserve

Mode Register Set

CK,CK

Mode

Precharge

All Banks

Any

Command

t_MRD

tCK

tRP

V58C265164S Rev. 1.7 August 2001

1...3 4 567 8 9...44

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