V58C3643204SAT
PRELIMINARY
HIGH PERFORMANCE
3.3 VOLT 2M X 32 DDR SDRAM
4 X 512K X 32
45
50
55
60
System Frequency (fCK
)
225MHz
200 MHz
5 ns
183 MHz
5.5 ns
166 MHz
6 ns
Clock Cycle Time (tCK3
Clock Cycle Time (tCK4
)
)
4.5 ns
Features
Description
■ 4 banks x 512K x 32 organization
■ High speed data transfer rates with system
frequency up to 225 MHz
The V58C3643204SAT is a four bank DDR
DRAM organized as 4 banks x 512K x 32. The
V58C3643204SAT achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
■ Data Mask for Write Control (DM)
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 3, 4
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 full page for Sequential Type
2, 4, 8 full page for Interleave Type
■ Automatic and Controlled Precharge Command
■ Suspend Mode and Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 2048 cycles/16ms
■ Available in 100-pin TQFP
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
■ Differential clock inputs CLK and CLK
■ Power Supply 3.3V ± 0.3V
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
100-pin TQFP
-45
-50
-55
-60
Std.
L
0°C to 70°C
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•
•
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V58C3643204SAT Rev. 1.4 August 2001
1