Datasheet > V58C265804S

V58C265804S

更新时间： 2024-11-27 22:36:59

品牌	Logo	应用领域
MOSEL		动态存储器双倍数据速率
页数	文件大小	规格书
44页	458K
描述
HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

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中文翻译

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数据手册

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V58C265804S 数据手册

V58C265804S

PRELIMINARY

MOSEL VITELIC

HIGH PERFORMANCE

2.5 VOLT 8M X 8 DDR SDRAM

4 BANKS X 2Mbit X 8

166 MHz

6 ns

System Frequency (f

)

143 MHz

7 ns

125 MHz

8 ns

Clock Cycle Time (t

)

CK3

)

6.5 ns

7ns

7.5 ns

8ns

9 ns

CK2.5

)

10ns

CK2

Features

Description

■ 4 banks x 2Mbit x 8 organization

■ High speed data transfer rates with system

frequency up to 166 MHz

The V58C265804S is a four bank DDR DRAM or-

ganized as 4 banks x 2Mbit x 8. The V58C265804S

achieves high speed data transfer rates by employ-

ing a chip architecture that prefetches multiple bits

and then synchronizes the output data to a system

clock

■ Data Mask for Write Control (DM)

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS Latency: 2, 2.5, 3

■ Programmable Wrap Sequence: Sequential

or Interleave

All of the control, address, circuits are synchro-

nized with the positive edge of an externally sup-

plied clock. I/O transactions are possible on both

edges of DQS.

■ Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at a higher rate than is possible with standard

DRAMs. A sequential and gapless data rate is pos-

sible depending on burst length, CAS latency and

speed grade of the device.

■ Automatic and Controlled Precharge Command

■ Suspend Mode and Power Down Mode

■ Auto Refresh and Self Refresh

■ Refresh Interval: 4096 cycles/64 ms

■ Available in 66-pin 400 mil TSOP-II

■ SSTL-2 Compatible I/Os

■ Double Data Rate (DDR)

■ Bidirectional Data Strobe (DQs) for input and

output data, active on both edges

■ On-Chip DLL aligns DQ and DQs transitions with

CLK transitions

■ Differential clock inputs CLK and CLK

■ Power Supply 2.5V ± 0.2V

Device Usage Chart

Operating

Temperature

Range

Package Outline

CLK Cycle Time (ns)

Power

Temperature

Mark

JEDEC 66 TSOP II

–6

-7

-8

Std.

0°C to 70 °C

•

Blank

V58C265804S Rev. 1.3 January 2000

12 3 4 5 6 7...44

中文翻译

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