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UPSD3253BV-24U6 PDF预览

UPSD3253BV-24U6

更新时间: 2024-10-13 22:13:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存微控制器和处理器外围集成电路静态存储器
页数 文件大小 规格书
176页 1203K
描述
Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM

UPSD3253BV-24U6 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-52
针数:52Reach Compliance Code:compliant
风险等级:5.82Is Samacsys:N
位大小:8CPU系列:8051
JESD-30 代码:S-PQFP-G52长度:12 mm
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP80,.55SQ,20
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not QualifiedRAM(字节):32768
ROM(单词):131072ROM可编程性:FLASH
座面最大高度:1.6 mm速度:24 MHz
子类别:Microcontrollers最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:12 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

UPSD3253BV-24U6 数据手册

 浏览型号UPSD3253BV-24U6的Datasheet PDF文件第2页浏览型号UPSD3253BV-24U6的Datasheet PDF文件第3页浏览型号UPSD3253BV-24U6的Datasheet PDF文件第4页浏览型号UPSD3253BV-24U6的Datasheet PDF文件第5页浏览型号UPSD3253BV-24U6的Datasheet PDF文件第6页浏览型号UPSD3253BV-24U6的Datasheet PDF文件第7页 
µPSD325X  
Flash Programmable System Devices  
with 8032 Microcontroller Core and 256Kbit SRAM  
FEATURES SUMMARY  
The µPSD325X devices combine a Flash PSD  
Figure 1. 52-lead, Thin, Quad, Flat Package  
architecture with an 8032 microcontroller core.  
The µPSD325X devices of Flash PSDs feature  
dual banks of Flash memory, SRAM, general  
purpose I/O and programmable logic, supervi-  
2
sory functions and access via USB, I C, ADC,  
DDC and PWM channels, and an on-board  
8032 microcontroller core, with two UARTs,  
three 16-bit Timer/Counters and two External  
Interrupts. As with other Flash PSD families, the  
µPSD325X devices are also in-system pro-  
grammable (ISP) via a JTAG ISP interface.  
TQFP52 (T)  
Large 32KByte SRAM with battery back-up  
option  
Dual bank Flash memories  
– 128KByte or 256KByte main Flash memory  
– 32KByte secondary Flash memory  
Content Security  
Figure 2. 80-lead, Thin, Quad, Flat Package  
– Block access to Flash memory  
Programmable Decode PLD for flexible address  
mapping of all memories within 8032 space.  
High-speed clock standard 8032 core (12-cycle)  
USB Interface (some devices only)  
2
I C interface for peripheral connections  
5 Pulse Width Modulator (PWM) channels  
Analog-to-Digital Converter (ADC)  
Standalone Display Data Channel (DDC)  
Six I/O ports with up to 50 I/O pins  
3000 gate PLD with 16 macrocells  
Supervisor functions with Watchdog Timer  
In-System Programming (ISP) via JTAG  
Zero-Power Technology  
TQFP80 (U)  
Single Supply Voltage  
– 4.5 to 5.5V  
– 3.0 to 3.6V  
November 2002  
1/176  

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