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UPD720201K8-701-BAC-A

更新时间： 2024-11-06 12:48:55

品牌	Logo	应用领域
瑞萨 - RENESAS		总线控制器微控制器和处理器光电二极管 PC
页数	文件大小	规格书
43页	1850K
描述
ASSP (USB3.0 HOST CONTROLLER)

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UPD720201K8-701-BAC-A 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.71	Samacsys Confidence：	3
Samacsys Status：	Released	Samacsys PartID：	989009
Samacsys Pin Count：	69	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Quad Flat No-Lead	Samacsys Footprint Name：	68-PIN QFN (8x8)
Samacsys Released Date：	2019-12-01 13:28:25	Is Samacsys：	N
JESD-30 代码：	S-PQCC-N68	端子数量：	68
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC68,.32SQ,16	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Bus Controllers
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	OTHER	端子形式：	NO LEAD
端子节距：	0.4 mm	端子位置：	QUAD
Base Number Matches：	1

UPD720201K8-701-BAC-A 数据手册

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Data Sheet

μPD720201/μPD720202

ASSP (USB3.0 HOST CONTROLLER)

R19DS0047EJ0500

Rev.5.00

Jan. 17, 2013

1. OVERVIEW

The μPD720201 and μPD720202 are Renesas’ third generation Universal Serial Bus 3.0 host controllers,

which comply with Universal Serial Bus 3.0 Specification, and Intel’s eXtensible Host Controller Interface

(xHCI). These devices reduce power consumption and offer a smaller package foot-print making them ideal

for designers who wish to add the USB3.0 interface to mobile computing devices such as laptops and

notebook computers.

The μPD720201 supports up to four USB3.0 SuperSpeed ports and the μPD720202 supports up to two

USB3.0 SuperSpeed ports. The μPD720201 and μPD720202 use a PCI Express® Gen 2 system interface

bus allowing system designers to easily add up to four (μPD720201) or two (μPD720202) USB3.0

SuperSpeed ports to systems containing the PCI Express bus interface. When connected to USB 3.0-

compliant peripherals, the μPD720201 and μPD720202 can transfer information at clock speeds of up to 5

Gbps. The μPD720201 and μPD720202 and USB3.0 standard are fully compliant and backward compatible

with the previous USB2.0 standard. The new USB3.0 standard supports data transfer speeds of up to ten

times faster than those of the previous-generation USB2.0 standard, enabling quick and efficient transfers of

large amounts of information.

1.1

Features

Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB

Implementers Forum, Inc

Supports the following speed data rate as follows: Low-Speed (1.5 Mbps) / Full-Speed (12

Mbps) / Hi-Speed (480 Mbps) / SuperSpeed (5 Gbps)

μPD720201 supports up to 4 downstream ports for all speeds

μPD720202 supports up to 2 downstream ports for all speeds

Supports all USB compliant data transfer types as follows; Control / Bulk / Interrupt /

Isochronous transfer

Compliant with Intel’s eXtensible Host Controller Interface (xHCI) Specification Revision 1.0

Supports USB debugging capability on all SuperSpeed ports.

Supports USB legacy function

Compliant with PCI Express Base Specification Revision 2.0

Supports Latency Tolerance Reporting ECN of PCI Express Specification

Supports ExpressCard^TMStandard Release1.0

Supports PCI Express Card Electromechanical Specification Revision 2.0

Supports PCI Bus Power Management Interface Specification Revision 1.2

Supports USB Battery Charging Specification Revision 1.2 and other portable devices

<R>

DCP mode of BC 1.2

CDP mode of BC 1.2

China Mobile Phone Chargers

EU Mobile Phone Chargers

Apple iOS products

Operational registers are direct-mapped to PCI memory space

Supports Serial Peripheral Interface (SPI) type ROM for Firmware

Supports Firmware Download Interface from system BIOS or system software

System clock: 24 MHz crystal

R19DS0047EJ0500 Rev. 5.00

Jan. 17, 2013

Page 1 of 40

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