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UPD703035AGF-XXX-3BA-A PDF预览

UPD703035AGF-XXX-3BA-A

更新时间： 2024-02-21 08:30:06
品牌 Logo 应用领域
日电电子 - NEC 时钟微控制器ISM频段外围集成电路
页数 文件大小 规格书
52页 640K
描述
Microcontroller, 32-Bit, MROM, 13MHz, MOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100

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UPD703035AGF-XXX-3BA-A 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFP包装说明：QFP,
针数：100Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.52
具有ADC：YES地址总线宽度：22
位大小：32最大时钟频率：13 MHz
DAC 通道：NODMA 通道：YES
外部数据总线宽度：16JESD-30 代码：R-PQFP-G100
JESD-609代码：e6长度：20 mm
I/O 线路数量：83端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：NO封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not QualifiedROM可编程性：MROM
座面最大高度：3 mm速度：13 MHz
最大供电电压：5.5 V最小供电电压：4 V
标称供电电压：5 V表面贴装：YES
技术：MOS温度等级：INDUSTRIAL
端子面层：TIN BISMUTH端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

UPD703035AGF-XXX-3BA-A 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD703034A, 703034AY, 703035A,  
703035AY, 70F3035A, 70F3035AY  
V850/SB2TM  
32-BIT SINGLE-CHIP MICROCONTROLLERS  
DESCRIPTION  
The µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY (V850/SB2) are 32-bit single-  
chip microcontrollers of the V850 FamilyTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial  
interfaces, A/D converter, DMA controller, and so on are integrated on a single chip.  
The µPD70F3035A and 70F3035AY have flash memory in place of the internal mask ROM of the µPD703035A  
and 703035AY. Because flash memory allows the program to be written and erased electrically with the device  
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale  
production, and rapid development of new products.  
The µPD703037A, 703037AY, 70F3037A, 70F3037AY, products with a different ROM/RAM size are also  
available.  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
V850/SB1TM, V850/SB2 User’s Manual Hardware: U13850E  
V850 Family User’s Manual Architecture:  
U10243E  
FEATURES  
{ Number of instructions: 74  
{ Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)  
{ General-purpose registers: 32 bits × 32 registers  
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,  
load/store instructions  
{ Memory space: 16 MB linear address space  
{ Internal memory ROM: 128 KB (µPD703034A, 703034AY: mask ROM)  
256 KB (µPD703035A, 703035AY: mask ROM)  
256 KB (µPD70F3035A, 70F3035AY: flash memory)  
RAM: 12 KB (µPD703034A, 703034AY)  
16 KB (µPD703035A, 703035AY, 70F3035A, 70F3035AY)  
{ Interrupt/exception: µPD703034A, 703035A, 70F3035A (external: 8, internal: 33 sources, exception: 1 source)  
µPD703034AY, 703035AY, 70F3035AY (external: 8, internal: 34 sources, exception: 1 source)  
{ I/O lines Total: 83  
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)  
8-bit timer (6 channels: TM2 to TM7)  
{ Watch timer: 1 channel  
{ Watchdog timer: 1 channel  
{ IEBusTM controller: 1 channel  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U14780EJ2V1DS00 (2nd edition)  
Date Published December 2001 N CP(K)  
Printed in Japan  
©
2000  
1234567...52

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