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UPD488448FB-C60-53-DQ1 PDF预览

UPD488448FB-C60-53-DQ1

更新时间： 2024-11-19 22:24:39
品牌 Logo 应用领域
日电电子 - NEC 内存集成电路动态存储器时钟
页数 文件大小 规格书
80页 1892K
描述
128 M-bit Direct Rambus⑩ DRAM

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD488448 for Rev. P  
™
128 M-bit Direct Rambus DRAM  
Description  
The Direct Rambus DRAM (Direct RDRAM ) is a general purpose high-performance memory device suitable for  
use in a broad range of applications including computer memory, graphics, video, and any other application where  
high bandwidth and low latency are required.  
The PD488448 is 128M-bit Direct Rambus DRAM (RDRAM ), organized as 8M words by 16 bits.  
µ
The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using  
conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers  
at 1.25 ns per two bytes (10 ns per sixteen bytes).  
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly  
addressed memory transactions. The separate control and data buses with independent row and column control  
yield over 95% bus efficiency. The Direct RDRAM’s thirty-two banks support up to four simultaneous transactions.  
System oriented features for mobile, graphics and large memory systems include power management, byte  
masking.  
The PD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and  
µ
mobile applications. Direct RDRAMs operate from a 2.5 volt supply.  
Features  
Highest sustained bandwidth per DRAM device  
•
- 1.6 GB/s sustained data transfer rate  
- Separate control and data buses for maximized efficiency  
- Separate row and column control buses for easy scheduling and highest performance  
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates  
Low latency features  
•
- Write buffer to reduce read latency  
- 3 precharge mechanisms for controller flexibility  
- Interleaved transactions  
Advanced power management:  
•
- Multiple low power states allows flexibility in power consumption versus time to transition to active state  
- Power-down self-refresh  
Overdrive current mode  
•
•
•
•
Organization: 1 Kbyte pages and 32 banks, x 16  
Uses Rambus Signaling Level (RSL) for up to 800 MHz operation  
Package : 62-pin TAPE FBGA ( BGA ) and 62-pin PLASTIC FBGA (D2BGA (Die Dimension Ball Grid Array) )  
µ
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. M14837EJ3V0DS00 (3rd edition)  
Date Published August 2000 NS CP (K)  
Printed in Japan  
The mark • shows major revised points.  
2000  
©
1234567...80

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