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UPD488588FF-C71-45-DH1 PDF预览

UPD488588FF-C71-45-DH1

更新时间： 2024-11-20 21:17:19
品牌 Logo 应用领域
尔必达 - ELPIDA 时钟动态存储器内存集成电路
页数 文件大小 规格书
79页 1256K
描述
Rambus DRAM, 16MX18, 45ns, CMOS, PBGA80, FBGA-80

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UPD488588FF-C71-45-DH1 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：TFBGA, BGA80,10X18,32
针数：80Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.28
风险等级：5.92Is Samacsys：N
访问模式：MULTI BANK PAGE BURST最长访问时间：45 ns
其他特性：SELF CONTAINED REFRESH最大时钟频率 (fCLK)：711 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B80
JESD-609代码：e0长度：17.16 mm
内存密度：301989888 bit内存集成电路类型：RAMBUS DRAM
内存宽度：18功能数量：1
端口数量：1端子数量：80
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS组织：16MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装等效代码：BGA80,10X18,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
电源：1.8/2.5,2.5 V认证状态：Not Qualified
座面最大高度：1.06 mm自我刷新：YES
子类别：DRAMs最大供电电压 (Vsup)：2.63 V
最小供电电压 (Vsup)：2.37 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
宽度：10.2 mmBase Number Matches：1

UPD488588FF-C71-45-DH1 数据手册

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DATA SHEET  
288M bits Direct Rambus DRAM  
µPD488588 (512K words × 18 bits × 32s banks)  
Description  
Features  
The Direct Rambus DRAM (Direct RDRAM) is a  
general purpose high-performance memory device  
suitable for use in a broad range of applications  
including computer memory, graphics, video, and any  
other application where high bandwidth and low latency  
are required.  
• Highest sustained bandwidth per DRAM device  
— 1.6 GB/s sustained data transfer rate  
— Separate control and data buses for maximized  
efficiency  
— Separate row and column control buses for easy  
scheduling and highest performance  
The µPD488588 is 288Mbits Direct Rambus DRAM  
— 32 banks: four transactions can take place  
simultaneously at full bandwidth data rates  
(RDRAM), organized as 16M words by 18 bits.  
The use of Rambus Signaling Level (RSL) technology  
permits 600MHz to 800MHz transfer rates while using  
conventional system and board design technologies.  
Direct RDRAM devices are capable of sustained data  
transfers at 1.25ns per two bytes (10ns per sixteen  
bytes).  
• Low latency features  
— Write buffer to reduce read latency  
— 3 precharge mechanisms for controller flexibility  
— Interleaved transactions  
• Advanced power management:  
— Multiple low power states allows flexibility in power  
consumption versus time to active state  
The architecture of the Direct RDRAMs allows the  
highest sustained bandwidth for multiple, simultaneous  
randomly addressed memory transactions.  
— Power-down self-refresh  
• Overdrive current mode  
The separate control and data buses with independent  
row and column control yield over 95% bus efficiency.  
The Direct RDRAM’s four banks support up to four  
simultaneous transactions.  
• Organization: 2K bytes pages and 32 banks, x 18  
• Uses Rambus Signaling Level (RSL) for up to  
800MHz operation  
System oriented features for mobile, graphics and large  
memory systems include power management, byte  
masking.  
• Package : 80-ball FBGA  
The µPD488588 is offered in a CSP horizontal package  
suitable for desktop as well as low-profile add-in card  
and mobile applications. Direct RDRAMs operate from  
a 2.5V supply.  
Document No. E0039N41 (Ver. 4.1)  
Date Published February 2006 (K) Japan  
URL: http://www.elpida.com  
This product became EOL in September, 2003.  
Elpida Memory, Inc. 2001-2006  
NEC Corporation 2000  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  
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