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UPD46185362BF1-E40-EQ1-A PDF预览

UPD46185362BF1-E40-EQ1-A

更新时间: 2024-11-14 05:18:43
品牌 Logo 应用领域
瑞萨 - RENESAS 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
36页 637K
描述
QDRII/DDRII/ QDRII+/DDRII+ SRAM, LBGA, /Tray

UPD46185362BF1-E40-EQ1-A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LBGA
包装说明:BGA-165针数:165
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:0.45 nsJESD-30 代码:R-PBGA-B165
长度:15 mm内存密度:18874368 bit
内存集成电路类型:QDR SRAM内存宽度:36
功能数量:1端子数量:165
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX36
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL座面最大高度:1.46 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:13 mm
Base Number Matches:1

UPD46185362BF1-E40-EQ1-A 数据手册

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Datasheet  
μPD46185092B  
μPD46185182B  
μPD46185362B  
R10DS0112EJ0200  
Rev.2.00  
18M-BIT QDRTM II SRAM  
2-WORD BURST OPERATION  
Nov 09, 2012  
Description  
The μPD46185092B is a 2,097,152-word by 9-bit, the μPD46185182B is a 1,048,576-word by 18-bit and the  
μPD46185362B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS  
technology using full CMOS six-transistor memory cell.  
The μPD46185092B, μPD46185182B and μPD46185362B integrate unique synchronous peripheral circuitry and a  
burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and  
K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA (13 x 15)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR READ and WRITE operation  
Two-tick burst for low DDR transaction size  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time and clock skew matching-clock  
and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.  
User programmable impedance output (35 to 70 Ω)  
Fast clock cycle time : 3.3 ns (300 MHz), 2.0 ns (250 MHz)  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
R10DS0112EJ0200 Rev.2.00  
Nov 09, 2012  
Page 1 of 35  

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