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UPD45V128421G5-A75-9JF PDF预览

UPD45V128421G5-A75-9JF

更新时间: 2024-01-31 05:07:59
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
72页 443K
描述
Virtual Channel SDRAM

UPD45V128421G5-A75-9JF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON交错的突发长度:4
JESD-30 代码:R-PDSO-G54JESD-609代码:e0
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:54字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32MX4输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
子类别:DRAMs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

UPD45V128421G5-A75-9JF 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD45V128421, 45V128821, 45V128161  
128M-BIT VirtualChannelTM DRAM  
Description  
The 128M-bit VirtualChannel DRAM is implemented to be 100% pin and package compatible to the industry  
standard SDRAM. It uses the same command protocol and interface as SDRAM. It also follows the same electrical  
and timing specifications of the SDRAM, such that it is possible for one product platform to be used with the  
VirtualChannel DRAM and non-VirtualChannel DRAM part.  
Features  
Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Dual internal banks controlled by Bank Select Address  
Sixteen Channels controlled by Channel Select Address  
Quad segments controlled by Segment Select Address  
Byte control (x16) by LDQM and UDQM  
Wrap sequence (Interleave)  
Burst length (4)  
Read latency (2)  
Prefetch Read latency (4) : For x4 bits organization(µPD45V128421), prefetch read operation can not be used.  
Auto precharge and without auto precharge  
Auto refresh and Self refresh  
x4, x8, x16 organization  
Single 3.3 V 0.3 V power supply  
±
Interface: LVTTL  
Refresh cycle: 4K cycles / 64 ms  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0025N10 (1st edition)  
(Previous No. M15076EJ2V0DS00)  
Date Published January 2001 CP (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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