Datasheet > UPD4482183GF-A60

UPD4482183GF-A60

更新时间： 2024-11-06 20:32:27

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器内存集成电路
页数	文件大小	规格书
28页	255K
描述
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

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UPD4482183GF-A60 数据手册

DATA SHEET

MOS INTEGRATED CIRCUIT

PD4482163, 4482183, 4482323, 4482363

8M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

DOUBLE CYCLE DESELECT

Description

The μPD4482163 is a 524,288-word by 16-bit, the μPD4482183 is a 524,288-word by 18-bit, μPD4482323 is a 262,144-

word by 32-bit and the μPD4482363 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS

technology using Full-CMOS six-transistor memory cell.

The μPD4482163, μPD4482183, μPD4482323 and μPD4482363 integrates unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single

clock input (CLK).

The μPD4482163, μPD4482183, μPD4482323 and μPD4482363 are suitable for applications which require synchronous

operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The μPD4482163, μPD4482183, μPD4482323 and μPD4482363 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm

package thickness for high density and low capacitive loading.

Features

• Single 3.3 V power supply

• Synchronous operation

• Operating temperature : T_A= 0 to 70 °C (-A44, -A50, -A60)

T_A= −40 to +85 °C (-A44Y, -A50Y, -A60Y)

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for pipelined operation

• Double-Cycle deselect timing

• All registers triggered off positive clock edge

• 3.3 V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4, /BWE (μPD4482323, μPD4482363)

/BW1, /BW2, /BWE (μPD4482163, μPD4482183)

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M14904EJ4V0DS00 (4th edition)

Date Published February 2006 NS CP(K)

Printed in Japan

The mark shows major revised points.

2000

The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

12 3 4 5 6 7...28

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与UPD4482183GF-A60相关器件

型号	品牌	获取价格	描述	数据表
UPD4482183GF-A60Y	NEC	获取价格	8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT
UPD4482183GF-A60Y-A	NEC	获取价格	暂无描述
UPD4482321	NEC	获取价格	8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482321GF-A65	NEC	获取价格	8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482321GF-A65-A	NEC	获取价格	暂无描述
UPD4482321GF-A65Y	NEC	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD4482321GF-A65Y-A	NEC	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD4482321GF-A75	NEC	获取价格	8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482321GF-A75-A	NEC	获取价格	暂无描述
UPD4482321GF-A75Y	NEC	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

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