5秒后页面跳转
UPD44324085F5-E40-EQ2-A PDF预览

UPD44324085F5-E40-EQ2-A

更新时间: 2024-10-15 13:01:31
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
32页 351K
描述
暂无描述

UPD44324085F5-E40-EQ2-A 数据手册

 浏览型号UPD44324085F5-E40-EQ2-A的Datasheet PDF文件第2页浏览型号UPD44324085F5-E40-EQ2-A的Datasheet PDF文件第3页浏览型号UPD44324085F5-E40-EQ2-A的Datasheet PDF文件第4页浏览型号UPD44324085F5-E40-EQ2-A的Datasheet PDF文件第5页浏览型号UPD44324085F5-E40-EQ2-A的Datasheet PDF文件第6页浏览型号UPD44324085F5-E40-EQ2-A的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD44324085, 44324095, 44324185, 44324365  
36M-BIT DDRII SRAM SEPARATE I/O  
2-WORD BURST OPERATION  
Description  
The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a  
2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM  
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The µPD44324085, µPD44324095, µPD44324185 and µPD44324365 integrate unique synchronous peripheral circuitry  
and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K  
and /K.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC FBGA.  
Features  
1.8 ± 0.1 V power supply and HSTL I/O  
DLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports  
DDR read or write operation initiated each cycle  
Pipelined double data rate operation  
Separate data input/output bus  
Two-tick burst for low DDR transaction size  
Two input clocks (K and /K) for precise DDR timing at clock rising edges only  
Two output clocks (C and /C) for precise flight time and clock skew matching-clock  
and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability with µs restart  
User programmable impedance output  
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M16782EJ1V0DS00 (1st edition)  
Date Published October 2004 NS CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
2003  

与UPD44324085F5-E40-EQ2-A相关器件

型号 品牌 获取价格 描述 数据表
UPD44324085F5-E40Y-EQ2-A RENESAS

获取价格

4MX8 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, FBGA-165
UPD44324085F5-E50-EQ2 NEC

获取价格

36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
UPD44324085F5-E50-EQ2-A NEC

获取价格

DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, FBGA-165
UPD44324085F5-E50-EQ2-A RENESAS

获取价格

暂无描述
UPD44324085F5-E50Y-EQ2-A RENESAS

获取价格

4MX8 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, FBGA-165
UPD44324092BF5-E33-FQ1 RENESAS

获取价格

4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
UPD44324092BF5-E33-FQ1-A RENESAS

获取价格

4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44324092BF5-E33Y-FQ1-A RENESAS

获取价格

4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44324092BF5-E35Y-FQ1-A RENESAS

获取价格

4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44324092BF5-E40Y-FQ1 RENESAS

获取价格

4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165