Datasheet > UPD44164182F5-E30-EQ1

UPD44164182F5-E30-EQ1

更新时间： 2024-11-21 09:00:59

品牌	Logo	应用领域
瑞萨 - RENESAS		双倍数据速率静态存储器
页数	文件大小	规格书
32页	211K
描述
IC,SYNC SRAM,DDR,1MX18,CMOS,BGA,165PIN,PLASTIC

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中文翻译

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数据手册

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µPD44164082, 44164182, 44164362

18M-BIT DDRII SRAM

2-WORD BURST OPERATION

Description

The µPD44164082 is a 2,097,152-word by 8-bit, the µPD44164182 is a 1,048,576-word by 18-bit and the µPD44164362

is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using

full CMOS six-transistor memory cell.

The µPD44164082, µPD44164182 and µPD44164362 integrates unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.

These products are suitable for applications which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

• 1.8 ± 0.1 V power supply and HSTL I/O

• DLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability with µs restart

• User programmable impedence output

• Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15821EJ2V0DS00 (2nd edition)

Date Published April 2002 NS CP(K)

Printed in Japan

The mark shows major revised points.

2001

12 3 4 5 6 7...32

中文翻译

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与UPD44164182F5-E30-EQ1相关器件

型号	品牌	获取价格	描述	数据表
UPD44164182F5-E33-EQ1	RENESAS	获取价格	DDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
UPD44164182F5-E40-EQ1	NEC	获取价格	18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164182F5-E50-EQ1	NEC	获取价格	18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164182F5-E60-EQ1	NEC	获取价格	18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164184AF5-E33-EQ2-A	NEC	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184AF5-E37Y-EQ2	NEC	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164184AF5-E37Y-EQ2-A	NEC	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184AF5-E40-EQ2	NEC	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164184AF5-E40-EQ2-A	RENESAS	获取价格	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184AF5-E40-EQ2-A	NEC	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

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