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UPD44164184AF5-E40Y-EQ2 PDF预览

UPD44164184AF5-E40Y-EQ2

更新时间: 2024-11-21 09:23:15
品牌 Logo 应用领域
日电电子 - NEC 双倍数据速率静态存储器
页数 文件大小 规格书
40页 378K
描述
DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165

UPD44164184AF5-E40Y-EQ2 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
PD44164084A, 44164094A, 44164184A, 44164364A  
μ
18M-BIT DDRII SRAM  
4-WORD BURST OPERATION  
Description  
The μPD44164084A is a 2,097,152-word by 8-bit, the μPD44164094A is a 2,097,152-word by 9-bit, the μPD44164184A  
is a 1,048,576-word by 18-bit and the μPD44164364A is a 524,288-word by 36-bit synchronous double data rate static  
RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44164084A, μPD44164094A, μPD44164184A and μPD44164364A integrate unique synchronous peripheral  
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive  
edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA (13 x 15)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Pipelined double data rate operation  
Common data input/output bus  
Four-tick burst for reduced address frequency  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.  
User programmable impedance output  
<R>  
<R>  
Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
Operating ambient temperature: Commercial TA = 0 to +70°C  
(-E33, -E40, -E50)  
Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M17768EJ3V0DS00 (3rd edition)  
Date Published February 2007 NS CP(N)  
Printed in Japan  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  

与UPD44164184AF5-E40Y-EQ2相关器件

型号 品牌 获取价格 描述 数据表
UPD44164184AF5-E40Y-EQ2-A NEC

获取价格

DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184AF5-E50-EQ2-A NEC

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DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184AF5-E50Y-EQ2 NEC

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IC,SYNC SRAM,DDR,1MX18,CMOS,BGA,165PIN,PLASTIC
UPD44164184BF5-E33-EQ3 RENESAS

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1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164184BF5-E33-EQ3-A RENESAS

获取价格

1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184BF5-E33Y-EQ3 RENESAS

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1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164184BF5-E33Y-EQ3-A RENESAS

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1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184BF5-E35-EQ3 RENESAS

获取价格

1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164184BF5-E35-EQ3-A RENESAS

获取价格

1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164184BF5-E35Y-EQ3 RENESAS

获取价格

1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165