uP8003
Functional Description
The uP8003 is a highly integrated complete battery charger when interfacing toASIC.
specifically designed digital still camera where PCB is
specially concerned.
The USB_PWR can be turned off by pulling high the
USB_OFF pin. The USB_DET pin is pulled low when VUSB
is higher than its POR level and USB_OFF pin is pulled
high, no matter if WAKE_A/B are ready.
Supply Input Power for Charge Pump
The uP8003 integrates a charge pump that pumps
ADP_PWR, DOCK_PWR, or USB_PWR, whichever is System Power LDO
higher, to a 10V output voltage at CP pin for turning on the
An LDO regulates SYS_PWR voltage at 4.3V for system
internal power multiplexer and 4.3V LDO. The ramp up time
of the charge pump output voltage is highly dependent of
the capacitor attached to the CP pin. A 4.7nF capacitor
results in a typical 4.0ms ramp up time. The 4.3V LDO will
not be enabled until the charge pump voltage is higher than
9V.
power. The LDO will not be enabled until 1.) at least one
POR of supply inputs is recognized; 2.) charge pump output
VCP is higher than 9V; 3.) CHG_PWR voltage VCHG is higher
than 4.3V. The system power LDO features internal soft
start that minimizes the inrush current from supply inputs.
The output voltage ramp-up slew rate is about 1V/ms.
The charge pump is not designed to provide currents
for external circuits.
The uP8003 integrates two redundant system wake-up pins
for turning on/off the external PMOSFET pair as shown in
the typical application circuit. The PMOSFETs are turned
on by the pull-low resistor connected to the gates,
connecting battery to system power bus. When supply
inputs are available, the uP8003 switches the system power
bus from battery to supply input by turning off the
PMOSFETs and turning on the power multiplexer and LDO.
The system wake-up pins WAKE_Aand WAKE_B pull high
the gates CHG_PWR and turn off the PMOSFETs. Route
WAKE_Aand WAKE_B traces in parallel in real application.
Power Multiplexer
The uP8003 integrates a current-limited, break-before-make,
single-pole-triple-throw power multiplexer that selects
appropriate supply input according the availability of supply
inputs and default priority. The power multiplexer consists
of three body-diode-free NMOSFETs. The drains of the
NMOSFETs are connected toADP_PWR,DOCK_PWR and
USB_PWR pins respectively. The sources of the
NMOSFETs are connected to the CHG_PWR pin together.
Battery Charger
The supply inputs are monitored for power on reset (POR).
The CHG_PWR will not be enabled until at least one POR The uP8003 charges battery with a minimum current when
of the supply inputs is recognized. The POR threshold level the battery voltage is lower than 2.8V. The charger works at
is typically 4.4V at supply inputs rising. The input detection constant current mode when the battery voltage is between
output ADP_DET, DOCK_DET or USB_DET is pulled low 2.8V and 4.2V, the charge current is programmable up to
once its corresponding supply input is higher than the POR 1.5Aby an external resistor. The charger works at constant
threshold level and the WAKE_A/B are connected to voltage mode when the battery voltage is 4.2V. When the
CHG_PWR.
input voltage is removed, the uP8003 automatically enters
a low quiescent current sleep mode, dropping the battery
drain current to 1uA.
The default priority for the single-pole-triple-throw power
multiplexer isDOCK_PWR >ADP_PWR > USB_PWR. For
example, DOCK_PWR is selected if both ADP_PWR and Power On Reset at CHG_PWR pin
DOCK_PWR are both higher than their POR level.
The charger power CHG_PWR is continuously monitored
The power multiplexer is break-before-make type.Atypical for power on reset. The uP8003 resets itself as the
1us dead time is implemented when the multiplexer changes CHG_PWR voltage rises above the POR rising threshold,
its position. This ensures the NMOSFETs will not conduct typically 3.9V. The device shuts down if the CHG_PWR
simultaneously.
voltage is under its POR falling threshold, typically 3.8V.
The on-resistance of the ADP_PWR, DOCK_PWR and Chip Enable and 2.8V Bias Voltage
USB_PWR switches are 250mΩ typically.
The EN pin is internally pulled low 100kΩ to GND for chip
USB Power Monitoring and Control
disable/enable. Pulling this pin to ground shuts down the
uP8003 and disables the 2.8V bias voltage. When shut
down, the charger draws typically less than 30uA current
from the input power and less than 1uAfrom the battery.
A100kΩ + 100kΩ voltage divider from USB_PWR toGND
is included for USB power monitoring. The USB_MON is
the center of the voltage divider that makes VMON = VUSB/2.
Load effect of the USB_MON should be well considered Logic high of ENpin also enables the 2.8V bias voltage for
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P02, File Name: uP8003-DS-P0202
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