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UCC38500 PDF预览

UCC38500

更新时间： 2024-11-12 22:39:59
品牌 Logo 应用领域
德州仪器 - TI 功率因数校正控制器
页数 文件大小 规格书
8页 93K
描述
BiCMOS PFC/PWM Combination Controller

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中文翻译

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UCC38500 数据手册

 浏览型号UCC38500的Datasheet PDF文件第2页浏览型号UCC38500的Datasheet PDF文件第3页浏览型号UCC38500的Datasheet PDF文件第4页浏览型号UCC38500的Datasheet PDF文件第5页浏览型号UCC38500的Datasheet PDF文件第6页浏览型号UCC38500的Datasheet PDF文件第7页 
UCC18500/1/2/3  
UCC28500/1/2/3  
UCC38500/1/2/3  
PRELIMINARY  
BiCMOS PFC/PWM Combination Controller  
FEATURES  
• Combines PFC and 2nd Stage Down  
DESCRIPTION  
The UCC18500 family provides all of the functions necessary for an ac-  
tive power factor corrected preregulator and a second stage DC-to-DC  
converter. The controller achieves near-unity power factor by shaping  
the AC input line current waveform to correspond to the AC input line  
voltage using average current mode control. The DC-to-DC converter  
uses peak current mode control to perform the step down power con-  
version.  
Converter Function  
• Controls Boost PWM to Near-unity Power  
Factor  
• Accurate Power Limiting  
• Average Current Mode Control in PFC  
Stage  
The PFC stage is leading edge modulated while the second stage is  
trailing edge synchronized to allow for minimum overlap between the  
boost and PWM switches. This reduces ripple current in the bulk output  
capacitor.  
• Peak Current Mode Control in Second  
Stage  
• Programmable Oscillator  
In order to operate with a three to one range of input line voltages, a  
line feedforward (VFF) in used to keep input power constant with vary-  
ing input voltage. Generation of VFF is done using IAC in conjunction  
with an external single pole filter. This not only reduces external parts  
count, but avoids the use of high voltage components offering a lower  
cost solution. The multiplier then divides the line current by the square  
• Leading Edge/Trailing Edge Modulation  
for Reduced Output Ripple Using  
SmartSync™  
• Low Startup Supply Current  
• Synchronized Second Stage Start-up,  
with Programmable Soft-start  
of VFF  
.
(continued)  
• Programmable Second Stage Shut-down  
BLOCK DIAGRAM  
ISENSE2  
8
SS2  
13  
VCC  
9
GND  
6
VERR  
7
7.5V  
REFERENCE  
SECOND STAGE  
SOFT START  
20 VREF  
6.75V  
UVLO2  
1.5V  
UVLO  
16V/10  
VCC  
OVP/ENBL  
4
ENABLE  
–
+
I
LIMIT  
10  
GT2  
R
R
S
1.5V  
1.3V  
8.0V  
+
–
PFCOVP  
Q
ZERO  
VAOUT  
1
3
PWM  
CLK2  
POWER  
VOLTAGE  
ERROR AMP  
0.25V  
–
+
VSENSE  
–
+
X
VCC  
MULT  
CURRENT AMP  
÷
–
+
–
X
Q
S
PWM  
PWM  
+
7.5V  
12 GT1  
2
VFF 19  
OSC  
LATCH  
(V  
)
FF  
R
R
CLK1  
CLK2  
MIRROR  
2:1  
11 PWRGND  
CLK1  
CLK2  
I
LIMIT  
OSCILLATOR  
IAC 18  
14 PKLMT  
–
+
MOUT 17  
16  
15  
2
5
ISENSE1 CAOUT  
RT  
CT  
UDG-98189  
SLUS419 - AUGUST 1999  
12345678

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