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UCC1837DR PDF预览

UCC1837DR

更新时间: 2024-11-28 19:57:11
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管
页数 文件大小 规格书
8页 87K
描述
IC,VOLT REGULATOR,ADJUSTABLE,+1.5 TO +12V,BICMOS,SOP,8PIN,PLASTIC

UCC1837DR 技术参数

生命周期:Obsolete包装说明:SOP, SOP8,.25
Reach Compliance Code:unknown风险等级:5.84
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:R-PDSO-G8
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C最大输出电压:12 V
最小输出电压:1.5 V封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified子类别:Other Analog ICs
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

UCC1837DR 数据手册

 浏览型号UCC1837DR的Datasheet PDF文件第2页浏览型号UCC1837DR的Datasheet PDF文件第3页浏览型号UCC1837DR的Datasheet PDF文件第4页浏览型号UCC1837DR的Datasheet PDF文件第5页浏览型号UCC1837DR的Datasheet PDF文件第6页浏览型号UCC1837DR的Datasheet PDF文件第7页 
UCC1837  
UCC2837  
UCC3837  
8-Pin N-FET Linear Regulator Controller  
FEATURES  
DESCRIPTION  
On Board Charge Pump to Drive  
External N-MOSFET  
The UCC3837 Linear Regulator Controller includes all the features re-  
quired for an extremely low dropout linear regulator that uses an external  
N-channel MOSFET as the pass transistor. The device can operate from  
input voltages as low as 3V and can provide high current levels, thus pro-  
viding an efficient linear solution for custom processor voltages, bus ter-  
mination voltages, and other logic level voltages below 3V. The on board  
charge pump creates a gate drive voltage capable of driving an external  
N-MOSFET which is optimal for low dropout voltage and high efficiency.  
The wide versatility of this IC allows the user to optimize the setting of  
both current limit and output voltage for applications beyond or between  
standard 3-terminal linear regulator ranges.  
Input Voltage as Low as 3V  
Duty Ratio Mode Over Current  
Protection  
Extremely Low Dropout Voltage  
Low External Parts Count  
Output Voltages as Low as 1.5V  
This 8-pin controller IC features a duty ratio current limiting technique that  
provides peak transient loading capability while limiting the average  
power dissipation of the pass transistor during fault conditions. See the  
Application Section for detailed information.  
BLOCK DIAGRAM  
VDD  
1
CS  
8
CAP  
2
CHARGE  
PUMP  
LEVEL  
SHIFT  
5
6
VOUT  
FB  
CURRENT SENSE  
AMPLIFIER  
ERROR AMPLIFIER  
140mV  
UVLO  
1.5V REF  
CURRENT SENSE  
COMPARATOR  
100mV  
3
GND  
TIMER  
7
4
CT  
COMP  
UDG-99145  
SLUS228A - AUGUST 1999  

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