UCC18500DW

更新时间： 2024-02-16 05:04:26

品牌	Logo	应用领域
德州仪器 - TI		功率因数校正控制器
页数	文件大小	规格书
8页	93K
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中文翻译

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数据手册

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UCC18500DW 数据手册

UCC18500/1/2/3

UCC28500/1/2/3

UCC38500/1/2/3

PRELIMINARY

BiCMOS PFC/PWM Combination Controller

FEATURES

• Combines PFC and 2^ndStage Down

DESCRIPTION

The UCC18500 family provides all of the functions necessary for an ac-

tive power factor corrected preregulator and a second stage DC-to-DC

converter. The controller achieves near-unity power factor by shaping

the AC input line current waveform to correspond to the AC input line

voltage using average current mode control. The DC-to-DC converter

uses peak current mode control to perform the step down power con-

version.

Converter Function

• Controls Boost PWM to Near-unity Power

Factor

• Accurate Power Limiting

• Average Current Mode Control in PFC

Stage

The PFC stage is leading edge modulated while the second stage is

trailing edge synchronized to allow for minimum overlap between the

boost and PWM switches. This reduces ripple current in the bulk output

capacitor.

• Peak Current Mode Control in Second

Stage

• Programmable Oscillator

In order to operate with a three to one range of input line voltages, a

line feedforward (V_FF) in used to keep input power constant with vary-

ing input voltage. Generation of V_FFis done using I_ACin conjunction

with an external single pole filter. This not only reduces external parts

count, but avoids the use of high voltage components offering a lower

cost solution. The multiplier then divides the line current by the square

• Leading Edge/Trailing Edge Modulation

for Reduced Output Ripple Using

SmartSync™

• Low Startup Supply Current

• Synchronized Second Stage Start-up,

with Programmable Soft-start

of V_FF

(continued)

• Programmable Second Stage Shut-down

BLOCK DIAGRAM

ISENSE2

SS2

VCC

GND

VERR

7.5V

REFERENCE

SECOND STAGE

SOFT START

20 VREF

6.75V

UVLO2

1.5V

UVLO

16V/10

VCC

OVP/ENBL

ENABLE

–

LIMIT

GT2

1.5V

1.3V

8.0V

–

PFCOVP

ZERO

VAOUT

PWM

CLK2

POWER

VOLTAGE

ERROR AMP

0.25V

–

VSENSE

–

VCC

MULT

CURRENT AMP

–

PWM

7.5V

12 GT1

VFF 19

OSC

LATCH

)

CLK1

CLK2

MIRROR

2:1

11 PWRGND

CLK1

CLK2

LIMIT

OSCILLATOR

IAC 18

14 PKLMT

–

MOUT 17

ISENSE1 CAOUT

UDG-98189

SLUS419 - AUGUST 1999

12 3 4 5 6 7 8

中文翻译

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