Datasheet > UC5605PWPTR

UC5605PWPTR

更新时间： 2024-11-18 23:38:59

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
5页	268K
描述
Terminator

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UC5605PWPTR 数据手册

UC5605

9-Line Low Capacitance SCSI Active Terminator

FEATURES

DESCRIPTION

•

Reverse Disconnect

The UC5605 provides 9 lines of active termination for a SCSI (Small Computer

Systems Interface) parallel bus. The SCSI standard recommends active termi-

nation at both ends of the cable segment.

•

Complies with SCSI, SCSI-2

and SPI-2 Standards

The only functional differences between the UC5603 and UC5605 is the ab-

sence of the negative clamps on the output lines and the disconnect input must

be at a logic-low for the terminating resistors to be disconnected. Parametri-

cally, the UC5605 has a 5% tolerance on impedance and current compared to

a 3% tolerance on the UC5603. Custom power packages are utilized to allow

normal operation at full power (2 Watts).

•

5pF Channel Capacitance

during Disconnect

•

Hot Plugging Capability

−400mA Sourcing Current for

Termination

The UC5605 provides a disconnect feature which, when driven low, discon-

nects all terminating resistors, disables the regulator and greatly reduces

standby power consumption. The output channels remain high impedance even

without Termpwr applied. A low channel capacitance of 5pF allows interim

points of the bus to have little to no effect on the signal integrity.

•

+100mA Sinking Current for

Active Negation

•

1V Dropout Voltage Regulator

100µA Supply Current in

Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance,

and then most importantly, to trim the output current to a 5% tolerance, as close

to the maximum SCSI specification as possible. This maximizes the noise mar-

gin in fast SCSI operation. Other features include thermal shutdown and cur-

rent limit.

Disconnect Mode

•

Trimmed Termination Current

to 5%

•

Trimmed Impedance to 5%

This device is offered in low thermal resistance versions of the industry stand-

ard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin

TSSOP.

Low Thermal Resistance

Surface Mount Packages

BLOCK DIAGRAM

UDG-94122

Circuit Design Patented

3/97

12 3 4 5

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