Datasheet > UC5608QP

UC5608QP

更新时间： 2024-11-22 23:38:59

品牌	Logo	应用领域
其他 - ETC		接口集成电路
页数	文件大小	规格书
4页	251K
描述
Terminator

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数据手册

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UC5608QP 数据手册

UC5608

18-Line Low Capacitance SCSI Active Terminator

FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2 and SPI-2

Standards

The UC5608 provides 18 lines of active termination for a SCSI (Small

Computer Systems Interface) parallel bus. The SCSI standard recom-

mends active termination at both ends of the bus cable.

6pF Channel Capacitance during

Disconnect

The UC5608 is pin-for-pin compatible with its predecessors, the

UC5601 and UC5602 - 18 Line Active Terminator. Parametrically the

UC5608 has a 5% tolerance on impedance and current compared to a

3% tolerance on the UC5601 and the sink current is increased from

20 to 200mA. The low side clamps have been removed. Custom

power packages are utilized to allow normal operation at full power

conditions (2 Watts).

100µA Supply Current in Disconnect

Mode

•

Meets SCSI Hot Plugging Capability

−650mA Sourcing Current for

Termination

When in disconnect mode the terminator will disconnect all terminat-

ing resistors and disable the regulator, greatly reducing standby

power. The output channels remain high impedance even without

Termpwr applied.

•

+200mA Sinking Current for Active

Negation

•

Provides Active Termination for 18 Lines

Internal circuit trimming is utilized to trim the impedance to a 5% toler-

ance and, most importantly, to trim the output current to a 5% toler-

ance, as close to the max SCSI spec as possible, which maximizes

noise margin in fast SCSI operation.

Logic Command Disconnects all

Termination Lines

•

Trimmed Termination Current to 5%

Trimmed Impedance to 5%

Other features include 4.0 to 5.25V Termpwr, thermal shutdown and

current limit.

Current Limit and Thermal Shutdown

Protection

This device is offered in low thermal resistance versions of the indus-

try standard 28 pin wide body SOIC, 28 pin wide body TSSOP, and 28

pin PLCC, as well as 24 pin DIP.

BLOCK DIAGRAM

UDG-94047

Circuit Design Patented

3/97

12 3 4

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