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UC5612J

更新时间: 2024-11-22 23:38:59
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其他 - ETC 接口集成电路
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描述
Terminator

UC5612J 数据手册

 浏览型号UC5612J的Datasheet PDF文件第2页浏览型号UC5612J的Datasheet PDF文件第3页浏览型号UC5612J的Datasheet PDF文件第4页浏览型号UC5612J的Datasheet PDF文件第5页 
UC5612  
9-Line Low Capacitance SCSI Active Terminator  
FEATURES  
DESCRIPTION  
Complies with SCSI, SCSI-2  
and SPI-2 Standards  
The UC5612 provides 9 lines of active termination for a SCSI (Small Computer  
Systems Interface) parallel bus. The SCSI standard recommends active termi-  
nation at both ends of the cable segment.  
5pF Channel Capacitance  
during Disconnect  
The only functional differences between the UC5603 and UC5612 is the ab-  
sence of the negative clamps on the output lines. Parametrically, the UC5612  
has a 5% tolerance on impedance and current compared to a 3% tolerance on  
the UC5603. Custom power packages are utilized to allow normal operation at  
full power (2 Watts).  
Meets SCSI Hot Plugging  
400mA Sourcing Current for  
Termination  
The UC5612 provides a disconnect feature which, when opened or driven high,  
disconnects all terminating resistors, disables the regulator and greatly reduces  
standby power consumption. The output channels remain high impedance even  
without Termpwr applied. A low channel capacitance of 5pF allows interim  
points of the bus to have little to no effect on the signal integrity.  
+100mA Sinking Current for  
Active Negation  
1V Dropout Voltage Regulator  
Logic High Command  
Disconnects all Termination  
Lines  
Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance,  
and then most importantly, to trim the output current to a 5% tolerance, as close  
to the maximum SCSI specification as possible. This maximizes the noise mar-  
gin in fast SCSI operation. Other features include thermal shutdown and cur-  
rent limit.  
100µA Supply Current in  
Disconnect Mode  
Trimmed Termination Current  
to 5%  
This device is offered in low thermal resistance versions of the industry stand-  
ard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin  
TSSOP.  
Trimmed Impedance to 5%  
Low Thermal Resistance  
Surface Mount Packages  
BLOCK DIAGRAM  
UDG-94133  
Circuit Design Patented  
3/97  
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